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| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-05-10 20:27:34 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-05-10 20:27:34 +0000 |
| commit | 1a35b8e2eb165624013d5a2eaf8b673f026999fc (patch) | |
| tree | 7eae2722648cb2c06cbdaabb38fab7e8376fe001 /test/CodeGen/Hexagon | |
| parent | ed9fc9b8eef60e6305d1ba0fedd57e5b2bce3476 (diff) | |
| download | llvm-1a35b8e2eb165624013d5a2eaf8b673f026999fc.tar.gz llvm-1a35b8e2eb165624013d5a2eaf8b673f026999fc.tar.bz2 llvm-1a35b8e2eb165624013d5a2eaf8b673f026999fc.tar.xz | |
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
| -rw-r--r-- | test/CodeGen/Hexagon/pred-gp.ll | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/pred-gp.ll b/test/CodeGen/Hexagon/pred-gp.ll new file mode 100644 index 0000000000..299bd8679d --- /dev/null +++ b/test/CodeGen/Hexagon/pred-gp.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we are able to predicate instructions with gp-relative +; addressing mode. + +@d = external global i32 +@c = common global i32 0, align 4 + +; Function Attrs: nounwind +define i32 @test2(i8 zeroext %a, i8 zeroext %b) #0 { +; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}}) +; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}}) +entry: + %cmp = icmp eq i8 %a, %b + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %0 = load i32* @d, align 4 + store i32 %0, i32* @c, align 4 + br label %if.end + +if.end: + %1 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %0, %if.then ] + ret i32 %1 +} |