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| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-04-23 19:15:55 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-04-23 19:15:55 +0000 |
| commit | 47089c91aea7bdd8b2fa81223dfdd3484a20fd12 (patch) | |
| tree | 431ae19d77b29fa2ba54c2f7568f8252ea610338 /test/CodeGen/Hexagon | |
| parent | fa799112ddd69cebc6bacb9e24feb1298c9cdfb5 (diff) | |
| download | llvm-47089c91aea7bdd8b2fa81223dfdd3484a20fd12.tar.gz llvm-47089c91aea7bdd8b2fa81223dfdd3484a20fd12.tar.bz2 llvm-47089c91aea7bdd8b2fa81223dfdd3484a20fd12.tar.xz | |
Hexagon: Remove assembler mapped instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
| -rw-r--r-- | test/CodeGen/Hexagon/cmp_pred2.ll | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/cmp_pred2.ll b/test/CodeGen/Hexagon/cmp_pred2.ll new file mode 100644 index 0000000000..a20b9f09b6 --- /dev/null +++ b/test/CodeGen/Hexagon/cmp_pred2.ll @@ -0,0 +1,87 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Make sure that the assembler mapped compare instructions are correctly generated. + +@c = common global i32 0, align 4 + +define i32 @test1(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.ge +; CHECK: cmp.gt +entry: + %cmp = icmp slt i32 %a, 100 + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add nsw i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test2(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.lt +; CHECK: cmp.gt +entry: + %cmp = icmp sge i32 %a, %b + br i1 %cmp, label %entry.if.end_crit_edge, label %if.then + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add nsw i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test4(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.ltu +; CHECK: cmp.gtu +entry: + %cmp = icmp uge i32 %a, %b + br i1 %cmp, label %entry.if.end_crit_edge, label %if.then + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test5(i32 %a, i32 %b) nounwind { +; CHECK: cmp.gtu +entry: + %cmp = icmp uge i32 %a, 29999 + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} |