diff options
| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-02-20 16:13:27 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-02-20 16:13:27 +0000 |
| commit | d6c98ae63824854ea2175b362a10985cac7cfb32 (patch) | |
| tree | 677ad8b2b6e44be48a5fcb59a84b37042d1b71c3 /test/CodeGen/Hexagon | |
| parent | 6139b55222851e9fabde5c91de9e50ed8739c6c6 (diff) | |
| download | llvm-d6c98ae63824854ea2175b362a10985cac7cfb32.tar.gz llvm-d6c98ae63824854ea2175b362a10985cac7cfb32.tar.bz2 llvm-d6c98ae63824854ea2175b362a10985cac7cfb32.tar.xz | |
Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175634 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
| -rw-r--r-- | test/CodeGen/Hexagon/cext-check.ll | 57 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/dualstore.ll | 4 |
2 files changed, 59 insertions, 2 deletions
diff --git a/test/CodeGen/Hexagon/cext-check.ll b/test/CodeGen/Hexagon/cext-check.ll new file mode 100644 index 0000000000..7c4b19e5a4 --- /dev/null +++ b/test/CodeGen/Hexagon/cext-check.ll @@ -0,0 +1,57 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we constant extended instructions only when necessary. + +define i32 @cext_test1(i32* %a) nounwind { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+##8000) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000) +; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+##4092) +; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300) +entry: + %0 = load i32* %a, align 4 + %tobool = icmp ne i32 %0, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: + %arrayidx1 = getelementptr inbounds i32* %a, i32 2000 + %1 = load i32* %arrayidx1, align 4 + %add = add nsw i32 %1, 300000 + br label %return + +if.end: + %arrayidx2 = getelementptr inbounds i32* %a, i32 1023 + %2 = load i32* %arrayidx2, align 4 + %add3 = add nsw i32 %2, 300 + br label %return + +return: + %retval.0 = phi i32 [ %add, %if.then ], [ %add3, %if.end ] + ret i32 %retval.0 +} + +define i32 @cext_test2(i8* %a) nounwind { +; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+##1023) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+##1024) +; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##6000) +entry: + %tobool = icmp ne i8* %a, null + br i1 %tobool, label %if.then, label %if.end + +if.then: + %arrayidx = getelementptr inbounds i8* %a, i32 1023 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 300000 + br label %return + +if.end: + %arrayidx1 = getelementptr inbounds i8* %a, i32 1024 + %1 = load i8* %arrayidx1, align 1 + %conv2 = zext i8 %1 to i32 + %add3 = add nsw i32 %conv2, 6000 + br label %return + +return: + %retval.0 = phi i32 [ %add, %if.then ], [ %add3, %if.end ] + ret i32 %retval.0 +} diff --git a/test/CodeGen/Hexagon/dualstore.ll b/test/CodeGen/Hexagon/dualstore.ll index 067499530f..3bf60193a2 100644 --- a/test/CodeGen/Hexagon/dualstore.ll +++ b/test/CodeGen/Hexagon/dualstore.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s ; Check that we generate dual stores in one packet in V4 -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}#100000 -; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}#500000 +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000 +; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000 ; CHECK-NEXT: } @Reg = global i32 0, align 4 |