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authorAnton Korobeynikov <asl@math.spbu.ru>2009-10-10 22:17:47 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-10-10 22:17:47 +0000
commit8f8e9f08300f62db802767c9fb23b40aab66e51e (patch)
treeb078619524192d45acefb26c1e7abfdb9465a3e2 /test/CodeGen/MSP430
parent558c36729f8fb6606f06d034c5be6c83e4f4b509 (diff)
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It seems that OR operation does not affect status reg at all.
Remove impdef of SRW. This fixes PR4779 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83739 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MSP430')
-rw-r--r--test/CodeGen/MSP430/2009-10-10-OrImpDef.ll14
1 files changed, 14 insertions, 0 deletions
diff --git a/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll b/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
new file mode 100644
index 0000000000..856eb9db3f
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=msp430 < %s
+; PR4779
+define void @foo() nounwind {
+entry:
+ %r = alloca i8 ; <i8*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ volatile load i8* %r, align 1 ; <i8>:0 [#uses=1]
+ or i8 %0, 1 ; <i8>:1 [#uses=1]
+ volatile store i8 %1, i8* %r, align 1
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}