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| author | Reed Kotler <rkotler@mips.com> | 2013-08-16 23:05:18 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-08-16 23:05:18 +0000 |
| commit | 80f60610826158dcbfbeb5c235ca0ea673d23281 (patch) | |
| tree | 5cc9298fdfefc2de4049f5513bcd2aea2c4ad199 /test/CodeGen/Mips/ctlz.ll | |
| parent | 0c1c5b0aaac80ca233523379617df93bbc0e2014 (diff) | |
| download | llvm-80f60610826158dcbfbeb5c235ca0ea673d23281.tar.gz llvm-80f60610826158dcbfbeb5c235ca0ea673d23281.tar.bz2 llvm-80f60610826158dcbfbeb5c235ca0ea673d23281.tar.xz | |
Fix a subtle difference between running clang vs llc for mips16.
This regards how mips16 is viewed. It's not really a target type but
there has always been a target for it in the td files. It's more properly
-mcpu=mips32 -mattr=+mips16 . This is how clang treats it but we have
always had the -mcpu=mips16 which I probably should delete now but it will
require updating all the .ll test cases for mips16. In this case it changed
how we decide if we have a count bits instruction and whether instruction
lowering should then expand ctlz. Now that we have dual mode compilation,
-mattr=+mips16 really just indicates the inital processor mode that
we are compiling for. (It is also possible to have -mcpu=64 -mattr=+mips16
but as far as I know, nobody has even built such a processor, though there
is an architecture manual for this).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188586 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/ctlz.ll')
| -rw-r--r-- | test/CodeGen/Mips/ctlz.ll | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/ctlz.ll b/test/CodeGen/Mips/ctlz.ll new file mode 100644 index 0000000000..1b4b427e66 --- /dev/null +++ b/test/CodeGen/Mips/ctlz.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=static + +@x = global i32 28912, align 4 +@y = common global i32 0, align 4 + + +; Function Attrs: nounwind +define i32 @main() #0 { +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %0 = load i32* @x, align 4 + %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 true) + store i32 %1, i32* @y, align 4 + ret i32 0 +} + +; static: .end main + +; Function Attrs: nounwind readnone +declare i32 @llvm.ctlz.i32(i32, i1) #1 + + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #1 = { nounwind readnone } + |