diff options
author | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 19:09:21 +0000 |
---|---|---|
committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 19:09:21 +0000 |
commit | cb39aa05afd52f017869ce5399652223626da7b7 (patch) | |
tree | f1df198527bb7ce4dc83f9fde5a33d1726c29c73 /test/CodeGen/Mips/dsp-r1.ll | |
parent | 23bb38f034a7ff5566c2cea6b69645f4ca40307f (diff) | |
download | llvm-cb39aa05afd52f017869ce5399652223626da7b7.tar.gz llvm-cb39aa05afd52f017869ce5399652223626da7b7.tar.bz2 llvm-cb39aa05afd52f017869ce5399652223626da7b7.tar.xz |
MIPS DSP: ABSQ_S.PH instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/dsp-r1.ll')
-rw-r--r-- | test/CodeGen/Mips/dsp-r1.ll | 202 |
1 files changed, 202 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/dsp-r1.ll b/test/CodeGen/Mips/dsp-r1.ll index da9fbd0ebe..c49e4fc00c 100644 --- a/test/CodeGen/Mips/dsp-r1.ll +++ b/test/CodeGen/Mips/dsp-r1.ll @@ -996,3 +996,205 @@ entry: ret i32 %0 } +define { i32 } @test__builtin_mips_absq_s_ph1(i32 %i0, i32 %a0.coerce) nounwind { +entry: +; CHECK: absq_s.ph + + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = tail call <2 x i16> @llvm.mips.absq.s.ph(<2 x i16> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.absq.s.ph(<2 x i16>) nounwind + +define i32 @test__builtin_mips_absq_s_w1(i32 %i0, i32 %a0) nounwind { +entry: +; CHECK: absq_s.w + + %0 = tail call i32 @llvm.mips.absq.s.w(i32 %a0) + ret i32 %0 +} + +declare i32 @llvm.mips.absq.s.w(i32) nounwind + +define i32 @test__builtin_mips_preceq_w_phl1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: preceq.w.phl + + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = tail call i32 @llvm.mips.preceq.w.phl(<2 x i16> %0) + ret i32 %1 +} + +declare i32 @llvm.mips.preceq.w.phl(<2 x i16>) nounwind readnone + +define i32 @test__builtin_mips_preceq_w_phr1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: preceq.w.phr + + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = tail call i32 @llvm.mips.preceq.w.phr(<2 x i16> %0) + ret i32 %1 +} + +declare i32 @llvm.mips.preceq.w.phr(<2 x i16>) nounwind readnone + +define { i32 } @test__builtin_mips_precequ_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: precequ.ph.qbl + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_precequ_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: precequ.ph.qbr + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_precequ_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: precequ.ph.qbla + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_precequ_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: precequ.ph.qbra + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_preceu_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: preceu.ph.qbl + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_preceu_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: preceu.ph.qbr + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_preceu_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: preceu.ph.qbla + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_preceu_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone { +entry: +; CHECK: preceu.ph.qbra + + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8> %0) + %2 = bitcast <2 x i16> %1 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8>) nounwind readnone + +define { i32 } @test__builtin_mips_repl_qb1(i32 %i0) nounwind readnone { +entry: +; CHECK: repl.qb + + %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 127) + %1 = bitcast <4 x i8> %0 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +declare <4 x i8> @llvm.mips.repl.qb(i32) nounwind readnone + +define { i32 } @test__builtin_mips_repl_qb2(i32 %i0, i32 %a0) nounwind readnone { +entry: +; CHECK: replv.qb + + %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 %a0) + %1 = bitcast <4 x i8> %0 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +define { i32 } @test__builtin_mips_repl_ph1(i32 %i0) nounwind readnone { +entry: +; CHECK: repl.ph + + %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 0) + %1 = bitcast <2 x i16> %0 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone + +define { i32 } @test__builtin_mips_repl_ph2(i32 %i0, i32 %a0) nounwind readnone { +entry: +; CHECK: replv.ph + + %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 %a0) + %1 = bitcast <2 x i16> %0 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone { +entry: +; CHECK: bitrev + + %0 = tail call i32 @llvm.mips.bitrev(i32 %a0) + ret i32 %0 +} + +declare i32 @llvm.mips.bitrev(i32) nounwind readnone |