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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
| commit | f1ef27e6e308435035ffec112a6474ed5e009484 (patch) | |
| tree | e95a12e18af12ddcc5e485c2bce80ccbd3decd89 /test/CodeGen/Mips/msa/2rf_int_float.ll | |
| parent | d2a31a124f3bebbdfc4d886afe33a116893aa689 (diff) | |
| download | llvm-f1ef27e6e308435035ffec112a6474ed5e009484.tar.gz llvm-f1ef27e6e308435035ffec112a6474ed5e009484.tar.bz2 llvm-f1ef27e6e308435035ffec112a6474ed5e009484.tar.xz | |
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/msa/2rf_int_float.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/2rf_int_float.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll index 2e4244c854..f822a1cadc 100644 --- a/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,7 +2,7 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 |