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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-15 11:04:16 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-15 11:04:16 +0000 |
| commit | ca795b61be6274813b7c7bd2c63b60cf60f18462 (patch) | |
| tree | c9411e1f23b96a067b587b3d3b860f184f856e6f /test/CodeGen/Mips/msa/i5-s.ll | |
| parent | efbdf7f2320649512569143611f53177c27ba9f6 (diff) | |
| download | llvm-ca795b61be6274813b7c7bd2c63b60cf60f18462.tar.gz llvm-ca795b61be6274813b7c7bd2c63b60cf60f18462.tar.bz2 llvm-ca795b61be6274813b7c7bd2c63b60cf60f18462.tar.xz | |
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.
Summary:
This patch (correctly) breaks some MSA tests by exposing the cases when
SelectionDAG::getConstant() produces illegal types. These have been temporarily
marked XFAIL and the XFAIL flag will be removed when
SelectionDAG::getConstant() is fixed.
There are three categories of failure:
* Immediate instructions are not selected in one endian mode.
* Immediates used in ldi.[bhwd] must be different according to endianness.
(this only affects cases where the 'wrong' ldi is used to load the correct
bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...)))
* Non-immediate instructions that rely on immediates affected by the
previous two categories as part of their match pattern.
For example, the bset match pattern is the vector equivalent of
'ws | (1 << wt)'.
One test needed correcting to expect different output depending on whether big
or little endian was in use. This test was
test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category
of failure shown above. The little endian version of this test is named
basic_operations_little.ll and will be merged back into basic_operations.ll in
a follow up commit now that FileCheck supports multiple check prefixes.
Reviewers: bkramer, jacksprat, dsanders
Reviewed By: dsanders
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/msa/i5-s.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/i5-s.ll | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/i5-s.ll b/test/CodeGen/Mips/msa/i5-s.ll index 77f52bfb1a..60ba8e1e34 100644 --- a/test/CodeGen/Mips/msa/i5-s.ll +++ b/test/CodeGen/Mips/msa/i5-s.ll @@ -1,7 +1,12 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 's' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_subvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 |