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| author | Reed Kotler <rkotler@mips.com> | 2013-02-21 04:22:38 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-02-21 04:22:38 +0000 |
| commit | ffbe432595c78ba28c8a9d200bf92996eed5e5d9 (patch) | |
| tree | e8e487c8bd384da748598efd81d144d945c1e047 /test/CodeGen/Mips | |
| parent | b8ebc9e2444c73126bdc812165f808f22af10cfa (diff) | |
| download | llvm-ffbe432595c78ba28c8a9d200bf92996eed5e5d9.tar.gz llvm-ffbe432595c78ba28c8a9d200bf92996eed5e5d9.tar.bz2 llvm-ffbe432595c78ba28c8a9d200bf92996eed5e5d9.tar.xz | |
Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175718 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips')
| -rw-r--r-- | test/CodeGen/Mips/selpat.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/Mips/selpat.ll b/test/CodeGen/Mips/selpat.ll index cda0c96ef4..57cc126bed 100644 --- a/test/CodeGen/Mips/selpat.ll +++ b/test/CodeGen/Mips/selpat.ll @@ -67,7 +67,7 @@ entry: %2 = load i32* @f, align 4 %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: beqz ${{[0-9]+}}, .+4 +; 16: beqz ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %cmp1 = icmp eq i32 %3, 0 @@ -238,7 +238,7 @@ entry: %2 = load i32* @t, align 4 %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: bnez ${{[0-9]+}}, .+4 +; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %cmp1 = icmp ne i32 %3, 0 @@ -260,7 +260,7 @@ entry: %2 = load i32* @t, align 4 %cond = select i1 %tobool, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: bnez ${{[0-9]+}}, .+4 +; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %tobool1 = icmp ne i32 %3, 0 |