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| author | Jack Carter <jack.carter@imgtec.com> | 2013-03-04 21:33:15 +0000 |
|---|---|---|
| committer | Jack Carter <jack.carter@imgtec.com> | 2013-03-04 21:33:15 +0000 |
| commit | 0b9675d631a33ecde9e11febea48a2c6551bfeec (patch) | |
| tree | e89ab34429b1d4a6acc6c020459cb304e1ecdf59 /test/CodeGen/Mips | |
| parent | 75d0ad42150d2446cc3bd062a93b59e9e1dc759b (diff) | |
| download | llvm-0b9675d631a33ecde9e11febea48a2c6551bfeec.tar.gz llvm-0b9675d631a33ecde9e11febea48a2c6551bfeec.tar.bz2 llvm-0b9675d631a33ecde9e11febea48a2c6551bfeec.tar.xz | |
Mips specific inline assembler constraint 'R'
'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips')
| -rw-r--r-- | test/CodeGen/Mips/inlineasm_constraint.ll | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll index 5adec3bb29..8d30f45d84 100644 --- a/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -51,5 +51,14 @@ entry: ; CHECK: #NO_APP tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind +; Now R Which takes the address of c + %c = alloca i32, align 4 + store i32 -4469539, i32* %c, align 4 + %8 = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1 +; CHECK: #APP +; CHECK: lwl ${{[0-9]+}}, 1 + 0(${{[0-9]+}}) +; CHECK: lwr ${{[0-9]+}}, 2 + 0(${{[0-9]+}}) +; CHECK: #NO_APP + ret i32 0 } |