Revert r179420 and r179421.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 7 insertions, 106 deletions

diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll
index 2e5a9edc48..0752f69c3e 100644
--- a/test/CodeGen/Mips/dsp-patterns.ll
+++ b/test/CodeGen/Mips/dsp-patterns.ll
@@ -1,8 +1,7 @@
-; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
-; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
+; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
 
-; R1: test_lbux:
-; R1: lbux ${{[0-9]+}}
+; CHECK: test_lbux:
+; CHECK: lbux ${{[0-9]+}}
 
 define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
 entry:
@@ -11,8 +10,8 @@ entry:
   ret i8 %0
 }
 
-; R1: test_lhx:
-; R1: lhx ${{[0-9]+}}
+; CHECK: test_lhx:
+; CHECK: lhx ${{[0-9]+}}
 
 define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
 entry:
@@ -21,8 +20,8 @@ entry:
   ret i16 %0
 }
 
-; R1: test_lwx:
-; R1: lwx ${{[0-9]+}}
+; CHECK: test_lwx:
+; CHECK: lwx ${{[0-9]+}}
 
 define i32 @test_lwx(i32* nocapture %b, i32 %i) {
 entry:
@@ -30,101 +29,3 @@ entry:
   %0 = load i32* %add.ptr, align 4
   ret i32 %0
 }
-
-; R1: test_add_v2q15_:
-; R1: addq.ph ${{[0-9]+}}
-
-define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
-entry:
-  %0 = bitcast i32 %a.coerce to <2 x i16>
-  %1 = bitcast i32 %b.coerce to <2 x i16>
-  %add = add <2 x i16> %0, %1
-  %2 = bitcast <2 x i16> %add to i32
-  %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
-  ret { i32 } %.fca.0.insert
-}
-
-; R1: test_sub_v2q15_:
-; R1: subq.ph ${{[0-9]+}}
-
-define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
-entry:
-  %0 = bitcast i32 %a.coerce to <2 x i16>
-  %1 = bitcast i32 %b.coerce to <2 x i16>
-  %sub = sub <2 x i16> %0, %1
-  %2 = bitcast <2 x i16> %sub to i32
-  %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
-  ret { i32 } %.fca.0.insert
-}
-
-; R2: test_mul_v2q15_:
-; R2: mul.ph ${{[0-9]+}}
-
-; mul.ph is an R2 instruction. Check that multiply node gets expanded.
-; R1: test_mul_v2q15_:
-; R1: mul ${{[0-9]+}}
-; R1: mul ${{[0-9]+}}
-
-define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
-entry:
-  %0 = bitcast i32 %a.coerce to <2 x i16>
-  %1 = bitcast i32 %b.coerce to <2 x i16>
-  %mul = mul <2 x i16> %0, %1
-  %2 = bitcast <2 x i16> %mul to i32
-  %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
-  ret { i32 } %.fca.0.insert
-}
-
-; R1: test_add_v4i8_:
-; R1: addu.qb ${{[0-9]+}}
-
-define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
-entry:
-  %0 = bitcast i32 %a.coerce to <4 x i8>
-  %1 = bitcast i32 %b.coerce to <4 x i8>
-  %add = add <4 x i8> %0, %1
-  %2 = bitcast <4 x i8> %add to i32
-  %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
-  ret { i32 } %.fca.0.insert
-}
-
-; R1: test_sub_v4i8_:
-; R1: subu.qb ${{[0-9]+}}
-
-define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
-entry:
-  %0 = bitcast i32 %a.coerce to <4 x i8>
-  %1 = bitcast i32 %b.coerce to <4 x i8>
-  %sub = sub <4 x i8> %0, %1
-  %2 = bitcast <4 x i8> %sub to i32
-  %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
-  ret { i32 } %.fca.0.insert
-}
-
-; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
-; R2: test_mul_v4i8_:
-; R2: mul ${{[0-9]+}}
-; R2: mul ${{[0-9]+}}
-; R2: mul ${{[0-9]+}}
-; R2: mul ${{[0-9]+}}
-
-define { i32 } @test_mul_v4i8_(i32 %a.coerce, i32 %b.coerce) {
-entry:
-  %0 = bitcast i32 %a.coerce to <4 x i8>
-  %1 = bitcast i32 %b.coerce to <4 x i8>
-  %mul = mul <4 x i8> %0, %1
-  %2 = bitcast <4 x i8> %mul to i32
-  %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
-  ret { i32 } %.fca.0.insert
-}
-
-; R1: test_addsc:
-; R1: addsc ${{[0-9]+}}
-; R1: addwc ${{[0-9]+}}
-
-define i64 @test_addsc(i64 %a, i64 %b) #1 {
-entry:
-  %add = add nsw i64 %b, %a
-  ret i64 %add
-}
-