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authorHal Finkel <hfinkel@anl.gov>2013-03-15 05:06:04 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-15 05:06:04 +0000
commit0cfb42adb5072fb19a01dba3ea58a33fd5927947 (patch)
tree10dabd9db4af644892adfbb84017e89c87c5308c /test/CodeGen/PowerPC/2010-02-12-saveCR.ll
parentc6aa8348363c67d6ef1fac87e1d933742bf41403 (diff)
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Allocate the RS spill slot for any PPC function with spills and a large stack frame
For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/2010-02-12-saveCR.ll')
-rw-r--r--test/CodeGen/PowerPC/2010-02-12-saveCR.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index 433fe5cc2a..0da6e4351b 100644
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -9,12 +9,12 @@ entry:
;CHECK: mfcr r0
;CHECK: lis r2, 1
;CHECK: rlwinm r0, r0, 8, 0, 31
-;CHECK: ori r2, r2, 34524
+;CHECK: ori r2, r2, 34540
;CHECK: stwx r0, r1, r2
; Make sure that the register scavenger returns the same temporary register.
;CHECK: lis r2, 1
;CHECK: mfcr r0
-;CHECK: ori r2, r2, 34520
+;CHECK: ori r2, r2, 34536
;CHECK: rlwinm r0, r0, 12, 0, 31
;CHECK: stwx r0, r1, r2
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
@@ -26,7 +26,7 @@ entry:
return: ; preds = %entry
;CHECK: lis r2, 1
-;CHECK: ori r2, r2, 34524
+;CHECK: ori r2, r2, 34540
;CHECK: lwzx r0, r1, r2
;CHECK: rlwinm r0, r0, 24, 0, 31
;CHECK: mtcrf 32, r0