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authorHal Finkel <hfinkel@anl.gov>2013-03-28 03:38:16 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-28 03:38:16 +0000
commitd957f957eee12cf26a7160e6015f0a7c2629904f (patch)
tree698891f378a4ceea642fe9a8102173b0c6849efd /test/CodeGen/PowerPC/2010-02-12-saveCR.ll
parentd01efc737aad480eaaa1316b05b7165ce7c04c96 (diff)
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Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructions
There were a few places where kill flags were not being set correctly, and where 32-bit instruction variants were being used with 64-bit registers. After r178180, this code was being triggered causing llc to assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178220 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/2010-02-12-saveCR.ll')
-rw-r--r--test/CodeGen/PowerPC/2010-02-12-saveCR.ll7
1 files changed, 3 insertions, 4 deletions
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index 79e8f96b39..097611a761 100644
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -8,16 +8,15 @@ entry:
; Note that part of what is being checked here is proper register reuse.
; CHECK: mfcr [[T1:r[0-9]+]] ; cr2
; CHECK: lis [[T2:r[0-9]+]], 1
-; FIXME: There should only be one lis needed here!
-; CHECK: lis [[T3:r[0-9]+]], 1
; CHECK: addi r3, r1, 72
; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31
; CHECK: ori [[T2]], [[T2]], 34540
-; CHECK: ori [[T3]], [[T3]], 34536
; CHECK: stwx [[T1]], r1, [[T2]]
+; CHECK: lis [[T3:r[0-9]+]], 1
; CHECK: mfcr [[T4:r[0-9]+]] ; cr3
+; CHECK: ori [[T3]], [[T3]], 34536
; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31
-; CHECK: stwx r4, r1, [[T3]]
+; CHECK: stwx [[T4]], r1, [[T3]]
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]