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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 00:20:48 +0000 |
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| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 00:20:48 +0000 |
| commit | 4b87fb1a4beb773630b0e47a1f2885d935afef29 (patch) | |
| tree | 91302f9561549a4ee84ca381f3a5c3ea4f7caaab /test/CodeGen/PowerPC/spill-nor0.ll | |
| parent | ee6825dc5c530609b09067ae4a19d4d819da51b1 (diff) | |
| download | llvm-4b87fb1a4beb773630b0e47a1f2885d935afef29.tar.gz llvm-4b87fb1a4beb773630b0e47a1f2885d935afef29.tar.bz2 llvm-4b87fb1a4beb773630b0e47a1f2885d935afef29.tar.xz | |
Merging r200288:
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r200288 | hfinkel | 2014-01-28 00:32:58 -0500 (Tue, 28 Jan 2014) | 5 lines
Handle spilling the PPC GPRC_NOR0 register class
GPRC_NOR0 is not a subclass of GPRC (because it also contains the ZERO pseudo
register). As a result, we also need to check for it in the spilling code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205821 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/spill-nor0.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/spill-nor0.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/spill-nor0.ll b/test/CodeGen/PowerPC/spill-nor0.ll new file mode 100644 index 0000000000..65bdc09143 --- /dev/null +++ b/test/CodeGen/PowerPC/spill-nor0.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -O0 -mcpu=ppc64 | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @_ZN4llvm3sys17RunningOnValgrindEv() #0 { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: ; preds = %entry + ret void + +if.end: ; preds = %entry + %0 = call i64 asm sideeffect "mr 3,$1\0A\09mr 4,$2\0A\09rotldi 0,0,3 ; rotldi 0,0,13\0A\09rotldi 0,0,61 ; rotldi 0,0,51\0A\09or 1,1,1\0A\09mr $0,3", "=b,b,b,~{cc},~{memory},~{r3},~{r4}"(i32 0, i64* undef) #0 + unreachable + +; CHECK-LABEL: @_ZN4llvm3sys17RunningOnValgrindEv +; CHECK: stw +; CHECK: lwz +} + +attributes #0 = { nounwind } + |