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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2012-12-14 17:02:38 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2012-12-14 17:02:38 +0000 |
| commit | b453e16855f347e300f1dc0cd0dfbdd65c27b0d2 (patch) | |
| tree | b743e0bbee0e4509e09b0b4cbc19b2d4e5d14113 /test/CodeGen/PowerPC/tls-ie.ll | |
| parent | 79c3742620efccf7c36ea1738bb121ad70d644d0 (diff) | |
| download | llvm-b453e16855f347e300f1dc0cd0dfbdd65c27b0d2.tar.gz llvm-b453e16855f347e300f1dc0cd0dfbdd65c27b0d2.tar.bz2 llvm-b453e16855f347e300f1dc0cd0dfbdd65c27b0d2.tar.xz | |
This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/tls-ie.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/tls-ie.ll | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/test/CodeGen/PowerPC/tls-ie.ll b/test/CodeGen/PowerPC/tls-ie.ll index cc6f084efb..c5cfba7b3f 100644 --- a/test/CodeGen/PowerPC/tls-ie.ll +++ b/test/CodeGen/PowerPC/tls-ie.ll @@ -16,6 +16,7 @@ entry: ret i32 %0 } -; CHECK: ld [[REG:[0-9]+]], a@got@tprel(2) -; CHECK: add {{[0-9]+}}, [[REG]], a@tls +; CHECK: addis [[REG1:[0-9]+]], 2, a@got@tprel@ha +; CHECK: ld [[REG2:[0-9]+]], a@got@tprel@l([[REG1]]) +; CHECK: add {{[0-9]+}}, [[REG2]], a@tls |