Replace coff-/elf-dump with llvm-readobj

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 80 insertions, 217 deletions

diff --git a/test/CodeGen/PowerPC/mcm-obj-2.ll b/test/CodeGen/PowerPC/mcm-obj-2.ll
index 2dd1718ba7..bc60b3baf2 100644
--- a/test/CodeGen/PowerPC/mcm-obj-2.ll
+++ b/test/CodeGen/PowerPC/mcm-obj-2.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -O1 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck %s
+; RUN: llvm-readobj -r | FileCheck %s
 
 ; FIXME: When asm-parse is available, could make this an assembly test.
 
@@ -19,18 +19,11 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing function-scoped variable si.
 ;
-; CHECK:       Relocation 0
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM2:[0-9]+]]
-; CHECK-NEXT:  'r_type', 0x00000032
-; CHECK:       Relocation 1
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM2]]
-; CHECK-NEXT:  'r_type', 0x00000030
-; CHECK:       Relocation 2
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM2]]
-; CHECK-NEXT:  'r_type', 0x00000030
+; CHECK: Relocations [
+; CHECK:   Section (1) .text {
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
 
 @gi = global i32 5, align 4
 
@@ -45,18 +38,9 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing file-scope variable gi.
 ;
-; CHECK:       Relocation 3
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM3:[0-9]+]]
-; CHECK-NEXT:  'r_type', 0x00000032
-; CHECK:       Relocation 4
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM3]]
-; CHECK-NEXT:  'r_type', 0x00000030
-; CHECK:       Relocation 5
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM3]]
-; CHECK-NEXT:  'r_type', 0x00000030
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
 
 define double @test_double_const() nounwind {
 entry:
@@ -66,12 +50,5 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing a constant.
 ;
-; CHECK:       Relocation 6
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM4:[0-9]+]]
-; CHECK-NEXT:  'r_type', 0x00000032
-; CHECK:       Relocation 7
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM4]]
-; CHECK-NEXT:  'r_type', 0x00000030
-
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll
index 117c3b3343..720c5fb6dd 100644
--- a/test/CodeGen/PowerPC/mcm-obj.ll
+++ b/test/CodeGen/PowerPC/mcm-obj.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=MEDIUM %s
+; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s
 ; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=LARGE %s
+; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
 
 ; FIXME: When asm-parse is available, could make this an assembly test.
 
@@ -21,25 +21,15 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing external variable ei.
 ;
-; MEDIUM:       '.rela.text'
-; MEDIUM:       Relocation 0
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM1:[0-9]+]]
-; MEDIUM-NEXT:  'r_type', 0x00000032
-; MEDIUM:       Relocation 1
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM1]]
-; MEDIUM-NEXT:  'r_type', 0x00000040
+; MEDIUM:      Relocations [
+; MEDIUM:        Section (1) .text {
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
 ;
-; LARGE:       '.rela.text'
-; LARGE:       Relocation 0
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM1:[0-9]+]]
-; LARGE-NEXT:  'r_type', 0x00000032
-; LARGE:       Relocation 1
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM1]]
-; LARGE-NEXT:  'r_type', 0x00000040
+; LARGE:       Relocations [
+; LARGE:         Section (1) .text {
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
 
 @test_fn_static.si = internal global i32 0, align 4
 
@@ -54,26 +44,14 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing function-scoped variable si.
 ;
-; MEDIUM:       Relocation 2
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM2:[0-9]+]]
-; MEDIUM-NEXT:  'r_type', 0x00000032
-; MEDIUM:       Relocation 3
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM2]]
-; MEDIUM-NEXT:  'r_type', 0x00000030
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
 ;
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing function-scoped variable si.
 ;
-; LARGE:       Relocation 2
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM2:[0-9]+]]
-; LARGE-NEXT:  'r_type', 0x00000032
-; LARGE:       Relocation 3
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM2]]
-; LARGE-NEXT:  'r_type', 0x00000040
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
 
 @gi = global i32 5, align 4
 
@@ -88,26 +66,14 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing file-scope variable gi.
 ;
-; MEDIUM:       Relocation 4
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM3:[0-9]+]]
-; MEDIUM-NEXT:  'r_type', 0x00000032
-; MEDIUM:       Relocation 5
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM3]]
-; MEDIUM-NEXT:  'r_type', 0x00000030
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
 ;
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing file-scope variable gi.
 ;
-; LARGE:       Relocation 4
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM3:[0-9]+]]
-; LARGE-NEXT:  'r_type', 0x00000032
-; LARGE:       Relocation 5
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM3]]
-; LARGE-NEXT:  'r_type', 0x00000040
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
 
 define double @test_double_const() nounwind {
 entry:
@@ -117,26 +83,14 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing a constant.
 ;
-; MEDIUM:       Relocation 6
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM4:[0-9]+]]
-; MEDIUM-NEXT:  'r_type', 0x00000032
-; MEDIUM:       Relocation 7
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM4]]
-; MEDIUM-NEXT:  'r_type', 0x00000030
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
 ;
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing a constant.
 ;
-; LARGE:       Relocation 6
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM4:[0-9]+]]
-; LARGE-NEXT:  'r_type', 0x00000032
-; LARGE:       Relocation 7
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM4]]
-; LARGE-NEXT:  'r_type', 0x00000040
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
 
 define signext i32 @test_jump_table(i32 signext %i) nounwind {
 entry:
@@ -185,23 +139,11 @@ sw.epilog:                                        ; preds = %sw.bb3, %sw.default
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing a jump table address.
 ;
-; MEDIUM:       Relocation 8
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM5:[0-9]+]]
-; MEDIUM-NEXT:  'r_type', 0x00000032
-; MEDIUM:       Relocation 9
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM5]]
-; MEDIUM-NEXT:  'r_type', 0x00000040
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
 ;
-; LARGE:       Relocation 8
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM5:[0-9]+]]
-; LARGE-NEXT:  'r_type', 0x00000032
-; LARGE:       Relocation 9
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM5]]
-; LARGE-NEXT:  'r_type', 0x00000040
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
 
 @ti = common global i32 0, align 4
 
@@ -216,23 +158,11 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing tentatively declared variable ti.
 ;
-; MEDIUM:       Relocation 10
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM6:[0-9]+]]
-; MEDIUM-NEXT:  'r_type', 0x00000032
-; MEDIUM:       Relocation 11
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM6]]
-; MEDIUM-NEXT:  'r_type', 0x00000040
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
 ;
-; LARGE:       Relocation 10
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM6:[0-9]+]]
-; LARGE-NEXT:  'r_type', 0x00000032
-; LARGE:       Relocation 11
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM6]]
-; LARGE-NEXT:  'r_type', 0x00000040
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
 
 define i8* @test_fnaddr() nounwind {
 entry:
@@ -248,21 +178,8 @@ declare signext i32 @foo(i32 signext)
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing function address foo.
 ;
-; MEDIUM:       Relocation 12
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM7:[0-9]+]]
-; MEDIUM-NEXT:  'r_type', 0x00000032
-; MEDIUM:       Relocation 13
-; MEDIUM-NEXT:  'r_offset'
-; MEDIUM-NEXT:  'r_sym', 0x[[SYM7]]
-; MEDIUM-NEXT:  'r_type', 0x00000040
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
 ;
-; LARGE:       Relocation 12
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM7:[0-9]+]]
-; LARGE-NEXT:  'r_type', 0x00000032
-; LARGE:       Relocation 13
-; LARGE-NEXT:  'r_offset'
-; LARGE-NEXT:  'r_sym', 0x[[SYM7]]
-; LARGE-NEXT:  'r_type', 0x00000040
-
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
diff --git a/test/CodeGen/PowerPC/pr15359.ll b/test/CodeGen/PowerPC/pr15359.ll
index 12fa3e5ffb..df02dfcb5c 100644
--- a/test/CodeGen/PowerPC/pr15359.ll
+++ b/test/CodeGen/PowerPC/pr15359.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -O0 -mcpu=pwr7 -filetype=obj %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck %s
+; RUN: llvm-readobj -t | FileCheck %s
 
 target datalayout = "E-p:64:64:64-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
@@ -14,7 +14,9 @@ entry:
 
 ; Verify that nextIdx has symbol type TLS.
 ;
-; CHECK:    '.symtab'
-; CHECK:    'nextIdx'
-; CHECK:    'st_type', 0x6
-
+; CHECK:      Symbol {
+; CHECK:        Name: nextIdx
+; CHECK-NEXT:   Value:
+; CHECK-NEXT:   Size:
+; CHECK-NEXT:   Binding:
+; CHECK-NEXT:   Type: TLS
diff --git a/test/CodeGen/PowerPC/tls-gd-obj.ll b/test/CodeGen/PowerPC/tls-gd-obj.ll
index 00b537d532..ffc0db0d14 100644
--- a/test/CodeGen/PowerPC/tls-gd-obj.ll
+++ b/test/CodeGen/PowerPC/tls-gd-obj.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mcpu=pwr7 -O0 -filetype=obj -relocation-model=pic %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck %s
+; RUN: llvm-readobj -r | FileCheck %s
 
 ; Test correct relocation generation for thread-local storage using
 ; the general dynamic model and integrated assembly.
@@ -21,21 +21,11 @@ entry:
 ; and R_PPC64_TLSGD for accessing external variable a, and R_PPC64_REL24
 ; for the call to __tls_get_addr.
 ;
-; CHECK:       '.rela.text'
-; CHECK:       Relocation 0
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1:[0-9a-f]+]]
-; CHECK-NEXT:  'r_type', 0x00000052
-; CHECK:       Relocation 1
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x00000050
-; CHECK:       Relocation 2
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x0000006b
-; CHECK:       Relocation 3
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x{{[0-9a-f]+}}
-; CHECK-NEXT:  'r_type', 0x0000000a
-
+; CHECK: Relocations [
+; CHECK:   Section (1) .text {
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TLSGD          a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_REL24          __tls_get_addr
+; CHECK:   }
+; CHECK: ]
diff --git a/test/CodeGen/PowerPC/tls-ie-obj.ll b/test/CodeGen/PowerPC/tls-ie-obj.ll
index 3600cc52ba..0f7a352952 100644
--- a/test/CodeGen/PowerPC/tls-ie-obj.ll
+++ b/test/CodeGen/PowerPC/tls-ie-obj.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mcpu=pwr7 -O0 -filetype=obj %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck %s
+; RUN: llvm-readobj -r | FileCheck %s
 
 ; Test correct relocation generation for thread-local storage
 ; using the initial-exec model and integrated assembly.
@@ -20,17 +20,10 @@ entry:
 ; Verify generation of R_PPC64_GOT_TPREL16_DS and R_PPC64_TLS for
 ; accessing external variable a.
 ;
-; CHECK:       '.rela.text'
-; CHECK:       Relocation 0
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1:[0-9a-f]+]]
-; CHECK-NEXT:  'r_type', 0x0000005a
-; CHECK:       Relocation 1
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x00000058
-; CHECK:       Relocation 2
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x00000043
-
+; CHECK: Relocations [
+; CHECK:   Section (1) .text {
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA    a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TLS               a
+; CHECK:   }
+; CHECK: ]
diff --git a/test/CodeGen/PowerPC/tls-ld-obj.ll b/test/CodeGen/PowerPC/tls-ld-obj.ll
index c521ae405f..29ee876845 100644
--- a/test/CodeGen/PowerPC/tls-ld-obj.ll
+++ b/test/CodeGen/PowerPC/tls-ld-obj.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mcpu=pwr7 -O0 -filetype=obj -relocation-model=pic %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck %s
+; RUN: llvm-readobj -r | FileCheck %s
 
 ; Test correct relocation generation for thread-local storage using
 ; the local dynamic model.
@@ -22,29 +22,13 @@ entry:
 ; accessing external variable a, and R_PPC64_REL24 for the call to
 ; __tls_get_addr.
 ;
-; CHECK:       '.rela.text'
-; CHECK:       Relocation 0
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1:[0-9a-f]+]]
-; CHECK-NEXT:  'r_type', 0x00000056
-; CHECK:       Relocation 1
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x00000054
-; CHECK:       Relocation 2
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x0000006c
-; CHECK:       Relocation 3
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x{{[0-9a-f]+}}
-; CHECK-NEXT:  'r_type', 0x0000000a
-; CHECK:       Relocation 4
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x0000004d
-; CHECK:       Relocation 5
-; CHECK-NEXT:  'r_offset'
-; CHECK-NEXT:  'r_sym', 0x[[SYM1]]
-; CHECK-NEXT:  'r_type', 0x0000004b
-
+; CHECK: Relocations [
+; CHECK:   Section (1) .text {
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TLSLD          a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_REL24          __tls_get_addr
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA    a
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO    a
+; CHECK:   }
+; CHECK: ]