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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
| commit | 6b3f6a744a6d16c5d62dc3477186035e8a74a8e9 (patch) | |
| tree | 1ace9471553c04326bc676bbc6b2cea18352a250 /test/CodeGen/R600/literals.ll | |
| parent | 5519dc9de88b36a2250db0faaf78c55f5e2c4d00 (diff) | |
| download | llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.gz llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.bz2 llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.xz | |
Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/literals.ll')
| -rw-r--r-- | test/CodeGen/R600/literals.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/test/CodeGen/R600/literals.ll b/test/CodeGen/R600/literals.ll index 9f4660ab8d..77b168ebde 100644 --- a/test/CodeGen/R600/literals.ll +++ b/test/CodeGen/R600/literals.ll @@ -7,8 +7,7 @@ ; ADD_INT literal.x KC0[2].Z, 5 ; CHECK: @i32_literal -; CHECK: ADD_INT T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x -; CHECK-NEXT: LSHR +; CHECK: ADD_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x ; CHECK-NEXT: 5 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) { entry: @@ -24,8 +23,7 @@ entry: ; ADD literal.x KC0[2].Z, 5.0 ; CHECK: @float_literal -; CHECK: ADD T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x -; CHECK-NEXT: LSHR +; CHECK: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x ; CHECK-NEXT: 1084227584(5.0 define void @float_literal(float addrspace(1)* %out, float %in) { entry: |