diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2013-05-20 15:28:48 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-05-20 15:28:48 +0000 |
| commit | 4f8d90df4518f1ebcc798fdbf01358a1a45adca6 (patch) | |
| tree | 46b071144390b44b5fc73717631da6719f046072 /test/CodeGen/R600/rotr.ll | |
| parent | 5ad6d082fcba7ffaa2979a5cc6444141137d07dc (diff) | |
| download | llvm-4f8d90df4518f1ebcc798fdbf01358a1a45adca6.tar.gz llvm-4f8d90df4518f1ebcc798fdbf01358a1a45adca6.tar.bz2 llvm-4f8d90df4518f1ebcc798fdbf01358a1a45adca6.tar.xz | |
R600: Fix rotr.ll on non-asserts builds
The -debug-only option is only available on asserts builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182291 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/rotr.ll')
| -rw-r--r-- | test/CodeGen/R600/rotr.ll | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll index 8bb5eaec82..ff4da412d6 100644 --- a/test/CodeGen/R600/rotr.ll +++ b/test/CodeGen/R600/rotr.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=redwood -o - 2>&1 | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=SI -o - 2>&1 | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=SI-CHECK %s -; R600-CHECK: rotr ; R600-CHECK: @rotr ; R600-CHECK: BIT_ALIGN_INT -; SI-CHECK: rotr ; SI-CHECK: @rotr ; SI-CHECK: V_ALIGNBIT_B32 define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) { @@ -18,13 +16,11 @@ entry: ret void } -; R600-CHECK: rotr ; R600-CHECK: @rotl ; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x ; R600-CHECK-NEXT: 32 ; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[xyzw]}} -; SI-CHECK: rotr ; SI-CHECK: @rotl ; SI-CHECK: V_SUB_I32_e32 [[DST:VGPR[0-9]+]], 32, {{VGPR[0-9]+}} ; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}, [[DST]] |