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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-03 17:40:11 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-03 17:40:11 +0000 |
| commit | e7397ee81ad07cab36362bab5a086f20acc60a80 (patch) | |
| tree | 754e9a6f488a46ed07acb9ec250af60e950d0b14 /test/CodeGen/R600/rotr.ll | |
| parent | e86f9d70ca29429ea83bc2361cf908dc566783af (diff) | |
| download | llvm-e7397ee81ad07cab36362bab5a086f20acc60a80.tar.gz llvm-e7397ee81ad07cab36362bab5a086f20acc60a80.tar.bz2 llvm-e7397ee81ad07cab36362bab5a086f20acc60a80.tar.xz | |
R600/SI: Add a calling convention for compute shaders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/rotr.ll')
| -rw-r--r-- | test/CodeGen/R600/rotr.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll index efbdcbf22a..960d30d630 100644 --- a/test/CodeGen/R600/rotr.ll +++ b/test/CodeGen/R600/rotr.ll @@ -22,8 +22,8 @@ entry: ; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[XYZW]}} ; SI-CHECK: @rotl -; SI-CHECK: V_SUB_I32_e32 [[DST:VGPR[0-9]+]], 32, {{VGPR[0-9]+}} -; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}, [[DST]] +; SI-CHECK: V_SUB_I32_e64 [[DST:VGPR[0-9]+]], 32, {{[SV]GPR[0-9]+}} +; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, [SV]GPR[0-9]+, VGPR[0-9]+}}, [[DST]] define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: %0 = shl i32 %x, %y |