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| author | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:54 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:54 +0000 |
| commit | f94eea9e112a75d0d328f799dd889681094cee97 (patch) | |
| tree | d2f6b813ca5e523d542d22f063e495e6093453c6 /test/CodeGen/R600/shared-op-cycle.ll | |
| parent | bb25a01d232257b134f1f6a5810116cbb04b95b1 (diff) | |
| download | llvm-f94eea9e112a75d0d328f799dd889681094cee97.tar.gz llvm-f94eea9e112a75d0d328f799dd889681094cee97.tar.bz2 llvm-f94eea9e112a75d0d328f799dd889681094cee97.tar.xz | |
R600: Use shared op optimization when checking cycle compatibility
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189981 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/shared-op-cycle.ll')
| -rw-r--r-- | test/CodeGen/R600/shared-op-cycle.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/test/CodeGen/R600/shared-op-cycle.ll b/test/CodeGen/R600/shared-op-cycle.ll new file mode 100644 index 0000000000..c49b5f4bd1 --- /dev/null +++ b/test/CodeGen/R600/shared-op-cycle.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @main +; CHECK: MULADD_IEEE * +; CHECK-NOT: MULADD_IEEE * + +define void @main() { + %w0 = call float @llvm.R600.load.input(i32 3) + %w1 = call float @llvm.R600.load.input(i32 7) + %w2 = call float @llvm.R600.load.input(i32 11) + %sq0 = fmul float %w0, %w0 + %r0 = fadd float %sq0, 2.0 + %sq1 = fmul float %w1, %w1 + %r1 = fadd float %sq1, 2.0 + %sq2 = fmul float %w2, %w2 + %r2 = fadd float %sq2, 2.0 + %v0 = insertelement <4 x float> undef, float %r0, i32 0 + %v1 = insertelement <4 x float> %v0, float %r1, i32 1 + %v2 = insertelement <4 x float> %v1, float %r2, i32 2 + %res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2) + %vecres = insertelement <4 x float> undef, float %res, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.R600.load.input(i32) #1 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone } +attributes #2 = { readonly } +attributes #3 = { nounwind readonly }
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