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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
| commit | 6b3f6a744a6d16c5d62dc3477186035e8a74a8e9 (patch) | |
| tree | 1ace9471553c04326bc676bbc6b2cea18352a250 /test/CodeGen/R600/work-item-intrinsics.ll | |
| parent | 5519dc9de88b36a2250db0faaf78c55f5e2c4d00 (diff) | |
| download | llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.gz llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.bz2 llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.xz | |
Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/work-item-intrinsics.ll')
| -rw-r--r-- | test/CodeGen/R600/work-item-intrinsics.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll index 86195ae88a..7998983ab2 100644 --- a/test/CodeGen/R600/work-item-intrinsics.ll +++ b/test/CodeGen/R600/work-item-intrinsics.ll @@ -3,7 +3,7 @@ ; R600-CHECK: @ngroups_x ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].X +; R600-CHECK: MOV * [[VAL]], KC0[0].X ; SI-CHECK: @ngroups_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 0 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -17,7 +17,7 @@ entry: ; R600-CHECK: @ngroups_y ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].Y +; R600-CHECK: MOV * [[VAL]], KC0[0].Y ; SI-CHECK: @ngroups_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 1 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -31,7 +31,7 @@ entry: ; R600-CHECK: @ngroups_z ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].Z +; R600-CHECK: MOV * [[VAL]], KC0[0].Z ; SI-CHECK: @ngroups_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 2 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -45,7 +45,7 @@ entry: ; R600-CHECK: @global_size_x ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].W +; R600-CHECK: MOV * [[VAL]], KC0[0].W ; SI-CHECK: @global_size_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 3 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -59,7 +59,7 @@ entry: ; R600-CHECK: @global_size_y ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].X +; R600-CHECK: MOV * [[VAL]], KC0[1].X ; SI-CHECK: @global_size_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 4 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -73,7 +73,7 @@ entry: ; R600-CHECK: @global_size_z ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].Y +; R600-CHECK: MOV * [[VAL]], KC0[1].Y ; SI-CHECK: @global_size_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 5 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -87,7 +87,7 @@ entry: ; R600-CHECK: @local_size_x ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].Z +; R600-CHECK: MOV * [[VAL]], KC0[1].Z ; SI-CHECK: @local_size_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 6 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -101,7 +101,7 @@ entry: ; R600-CHECK: @local_size_y ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].W +; R600-CHECK: MOV * [[VAL]], KC0[1].W ; SI-CHECK: @local_size_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 7 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -115,7 +115,7 @@ entry: ; R600-CHECK: @local_size_z ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[2].X +; R600-CHECK: MOV * [[VAL]], KC0[2].X ; SI-CHECK: @local_size_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 8 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] |