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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-07-23 01:48:18 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-07-23 01:48:18 +0000 |
| commit | a7eea0568c16f8e25b9e3ba9b7b73ae506738b63 (patch) | |
| tree | 8ab89aff96013d9d79b54f451583c86597bf7cf8 /test/CodeGen/R600/work-item-intrinsics.ll | |
| parent | 125f9d0ca216e08ee07ec11f190395901f089deb (diff) | |
| download | llvm-a7eea0568c16f8e25b9e3ba9b7b73ae506738b63.tar.gz llvm-a7eea0568c16f8e25b9e3ba9b7b73ae506738b63.tar.bz2 llvm-a7eea0568c16f8e25b9e3ba9b7b73ae506738b63.tar.xz | |
R600: Use KCache for kernel arguments
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186918 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/work-item-intrinsics.ll')
| -rw-r--r-- | test/CodeGen/R600/work-item-intrinsics.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll index 46e3e54b9a..7998983ab2 100644 --- a/test/CodeGen/R600/work-item-intrinsics.ll +++ b/test/CodeGen/R600/work-item-intrinsics.ll @@ -3,7 +3,7 @@ ; R600-CHECK: @ngroups_x ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 0 +; R600-CHECK: MOV * [[VAL]], KC0[0].X ; SI-CHECK: @ngroups_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 0 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -17,7 +17,7 @@ entry: ; R600-CHECK: @ngroups_y ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 4 +; R600-CHECK: MOV * [[VAL]], KC0[0].Y ; SI-CHECK: @ngroups_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 1 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -31,7 +31,7 @@ entry: ; R600-CHECK: @ngroups_z ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 8 +; R600-CHECK: MOV * [[VAL]], KC0[0].Z ; SI-CHECK: @ngroups_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 2 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -45,7 +45,7 @@ entry: ; R600-CHECK: @global_size_x ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 12 +; R600-CHECK: MOV * [[VAL]], KC0[0].W ; SI-CHECK: @global_size_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 3 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -59,7 +59,7 @@ entry: ; R600-CHECK: @global_size_y ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 16 +; R600-CHECK: MOV * [[VAL]], KC0[1].X ; SI-CHECK: @global_size_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 4 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -73,7 +73,7 @@ entry: ; R600-CHECK: @global_size_z ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 20 +; R600-CHECK: MOV * [[VAL]], KC0[1].Y ; SI-CHECK: @global_size_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 5 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -87,7 +87,7 @@ entry: ; R600-CHECK: @local_size_x ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 24 +; R600-CHECK: MOV * [[VAL]], KC0[1].Z ; SI-CHECK: @local_size_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 6 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -101,7 +101,7 @@ entry: ; R600-CHECK: @local_size_y ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 28 +; R600-CHECK: MOV * [[VAL]], KC0[1].W ; SI-CHECK: @local_size_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 7 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] @@ -115,7 +115,7 @@ entry: ; R600-CHECK: @local_size_z ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] -; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 32 +; R600-CHECK: MOV * [[VAL]], KC0[2].X ; SI-CHECK: @local_size_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 8 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]] |