diff options
author | Tom Stellard <thomas.stellard@amd.com> | 2013-04-19 02:10:53 +0000 |
---|---|---|
committer | Tom Stellard <thomas.stellard@amd.com> | 2013-04-19 02:10:53 +0000 |
commit | 3abd23bac565cdb10fe6dc17e4ee0640462b5660 (patch) | |
tree | af6b21957c03401af45e850668c0a1578dddfe0e /test/CodeGen/R600 | |
parent | 9affd163611b90113406b8729cc591eaad4778fa (diff) | |
download | llvm-3abd23bac565cdb10fe6dc17e4ee0640462b5660.tar.gz llvm-3abd23bac565cdb10fe6dc17e4ee0640462b5660.tar.bz2 llvm-3abd23bac565cdb10fe6dc17e4ee0640462b5660.tar.xz |
R600: Reorganize lit tests and document how they should be organized
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179828 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600')
-rw-r--r-- | test/CodeGen/R600/README | 21 | ||||
-rw-r--r-- | test/CodeGen/R600/add.ll (renamed from test/CodeGen/R600/add.v4i32.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/and.ll (renamed from test/CodeGen/R600/and.v4i32.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/fadd.ll | 19 | ||||
-rw-r--r-- | test/CodeGen/R600/fadd.v4f32.ll | 15 | ||||
-rw-r--r-- | test/CodeGen/R600/fdiv.ll (renamed from test/CodeGen/R600/fdiv.v4f32.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/fmul.ll | 19 | ||||
-rw-r--r-- | test/CodeGen/R600/fp_to_sint.ll | 14 | ||||
-rw-r--r-- | test/CodeGen/R600/fp_to_uint.ll | 14 | ||||
-rw-r--r-- | test/CodeGen/R600/fsub.ll | 19 | ||||
-rw-r--r-- | test/CodeGen/R600/fsub.v4f32.ll | 15 | ||||
-rw-r--r-- | test/CodeGen/R600/i8-to-double-to-float.ll (renamed from test/CodeGen/R600/i8_to_double_to_float.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/jump-address.ll (renamed from test/CodeGen/R600/jump_address.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/load.constant_addrspace.f32.ll | 9 | ||||
-rw-r--r-- | test/CodeGen/R600/load.i8.ll | 10 | ||||
-rw-r--r-- | test/CodeGen/R600/load.ll | 20 | ||||
-rw-r--r-- | test/CodeGen/R600/loop-address.ll (renamed from test/CodeGen/R600/loop-adress.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/selectcc-cnd.ll (renamed from test/CodeGen/R600/selectcc_cnde.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/selectcc-cnde-int.ll (renamed from test/CodeGen/R600/selectcc_cnde_int.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/setcc.ll (renamed from test/CodeGen/R600/setcc.v4i32.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/sint_to_fp.ll | 14 | ||||
-rw-r--r-- | test/CodeGen/R600/store.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/R600/store.r600.ll | 22 | ||||
-rw-r--r-- | test/CodeGen/R600/store.v4f32.ll | 9 | ||||
-rw-r--r-- | test/CodeGen/R600/store.v4i32.ll | 9 | ||||
-rw-r--r-- | test/CodeGen/R600/udiv.ll (renamed from test/CodeGen/R600/udiv.v4i32.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/uint_to_fp.ll | 14 | ||||
-rw-r--r-- | test/CodeGen/R600/urem.ll (renamed from test/CodeGen/R600/urem.v4i32.ll) | 0 | ||||
-rw-r--r-- | test/CodeGen/R600/vec4-expand.ll | 53 |
29 files changed, 174 insertions, 128 deletions
diff --git a/test/CodeGen/R600/README b/test/CodeGen/R600/README new file mode 100644 index 0000000000..96998bba28 --- /dev/null +++ b/test/CodeGen/R600/README @@ -0,0 +1,21 @@ ++==============================================================================+ +| How to organize the lit tests | ++==============================================================================+ + +- If you write a test for matching a single DAG opcode or intrinsic, it should + go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll) + +- If you write a test that matches several DAG opcodes and checks for a single + ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g. + bfi_int.ll + +- For all other tests, use your best judgement for organizing tests and naming + the files. + ++==============================================================================+ +| Naming conventions | ++==============================================================================+ + +- Use dash '-' and not underscore '_' to separate words in file names, unless + the file is named after a DAG opcode or ISA instruction that has an + underscore '_' in its name. diff --git a/test/CodeGen/R600/add.v4i32.ll b/test/CodeGen/R600/add.ll index ac4a87417b..ac4a87417b 100644 --- a/test/CodeGen/R600/add.v4i32.ll +++ b/test/CodeGen/R600/add.ll diff --git a/test/CodeGen/R600/and.v4i32.ll b/test/CodeGen/R600/and.ll index 662085e2d6..662085e2d6 100644 --- a/test/CodeGen/R600/and.v4i32.ll +++ b/test/CodeGen/R600/and.ll diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll index d7d1b6572c..81a4fa5f92 100644 --- a/test/CodeGen/R600/fadd.ll +++ b/test/CodeGen/R600/fadd.ll @@ -1,8 +1,9 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; CHECK: @fadd_f32 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { +define void @fadd_f32() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) %r2 = fadd float %r0, %r1 @@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fadd_v4f32 +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float> addrspace(1) * %in + %b = load <4 x float> addrspace(1) * %b_ptr + %result = fadd <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fadd.v4f32.ll b/test/CodeGen/R600/fadd.v4f32.ll deleted file mode 100644 index 85dbfd52cb..0000000000 --- a/test/CodeGen/R600/fadd.v4f32.ll +++ /dev/null @@ -1,15 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 - %a = load <4 x float> addrspace(1) * %in - %b = load <4 x float> addrspace(1) * %b_ptr - %result = fadd <4 x float> %a, %b - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/fdiv.v4f32.ll b/test/CodeGen/R600/fdiv.ll index 79e677f541..79e677f541 100644 --- a/test/CodeGen/R600/fdiv.v4f32.ll +++ b/test/CodeGen/R600/fdiv.ll diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll index eb1d523c0b..7fd22d823d 100644 --- a/test/CodeGen/R600/fmul.ll +++ b/test/CodeGen/R600/fmul.ll @@ -1,8 +1,9 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; CHECK: @fmul_f32 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { +define void @fmul_f32() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) %r2 = fmul float %r0, %r1 @@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fmul_v4f32 +; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float> addrspace(1) * %in + %b = load <4 x float> addrspace(1) * %b_ptr + %result = fmul <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll new file mode 100644 index 0000000000..9c21ad24e5 --- /dev/null +++ b/test/CodeGen/R600/fp_to_sint.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @fp_to_sint_v4i32 +; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %value = load <4 x float> addrspace(1) * %in + %result = fptosi <4 x float> %value to <4 x i32> + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll new file mode 100644 index 0000000000..d91098f716 --- /dev/null +++ b/test/CodeGen/R600/fp_to_uint.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @fp_to_uint_v4i32 +; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %value = load <4 x float> addrspace(1) * %in + %result = fptoui <4 x float> %value to <4 x i32> + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index 591aa52676..812388b66f 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -1,8 +1,9 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; CHECK: @fsub_f32 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -define void @test() { +define void @fsub_f32() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) %r2 = fsub float %r0, %r1 @@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fsub_v4f32 +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float> addrspace(1) * %in + %b = load <4 x float> addrspace(1) * %b_ptr + %result = fsub <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fsub.v4f32.ll b/test/CodeGen/R600/fsub.v4f32.ll deleted file mode 100644 index 612a57e4b6..0000000000 --- a/test/CodeGen/R600/fsub.v4f32.ll +++ /dev/null @@ -1,15 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 - %a = load <4 x float> addrspace(1) * %in - %b = load <4 x float> addrspace(1) * %b_ptr - %result = fsub <4 x float> %a, %b - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/i8_to_double_to_float.ll b/test/CodeGen/R600/i8-to-double-to-float.ll index 39f33227fa..39f33227fa 100644 --- a/test/CodeGen/R600/i8_to_double_to_float.ll +++ b/test/CodeGen/R600/i8-to-double-to-float.ll diff --git a/test/CodeGen/R600/jump_address.ll b/test/CodeGen/R600/jump-address.ll index ae9c8bba4f..ae9c8bba4f 100644 --- a/test/CodeGen/R600/jump_address.ll +++ b/test/CodeGen/R600/jump-address.ll diff --git a/test/CodeGen/R600/load.constant_addrspace.f32.ll b/test/CodeGen/R600/load.constant_addrspace.f32.ll deleted file mode 100644 index 93627283bb..0000000000 --- a/test/CodeGen/R600/load.constant_addrspace.f32.ll +++ /dev/null @@ -1,9 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @test(float addrspace(1)* %out, float addrspace(2)* %in) { - %1 = load float addrspace(2)* %in - store float %1, float addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/load.i8.ll b/test/CodeGen/R600/load.i8.ll deleted file mode 100644 index b070dcd520..0000000000 --- a/test/CodeGen/R600/load.i8.ll +++ /dev/null @@ -1,10 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @test(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { - %1 = load i8 addrspace(1)* %in - %2 = zext i8 %1 to i32 - store i32 %2, i32 addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll new file mode 100644 index 0000000000..b03245ae87 --- /dev/null +++ b/test/CodeGen/R600/load.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; Load an i8 value from the global address space. +; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} + +define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { + %1 = load i8 addrspace(1)* %in + %2 = zext i8 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; Load a f32 value from the constant address space. +; CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}} + +define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) { + %1 = load float addrspace(2)* %in + store float %1, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/loop-adress.ll b/test/CodeGen/R600/loop-address.ll index dc9295e8e7..dc9295e8e7 100644 --- a/test/CodeGen/R600/loop-adress.ll +++ b/test/CodeGen/R600/loop-address.ll diff --git a/test/CodeGen/R600/selectcc_cnde.ll b/test/CodeGen/R600/selectcc-cnd.ll index f0a0f512ba..f0a0f512ba 100644 --- a/test/CodeGen/R600/selectcc_cnde.ll +++ b/test/CodeGen/R600/selectcc-cnd.ll diff --git a/test/CodeGen/R600/selectcc_cnde_int.ll b/test/CodeGen/R600/selectcc-cnde-int.ll index b38078e26d..b38078e26d 100644 --- a/test/CodeGen/R600/selectcc_cnde_int.ll +++ b/test/CodeGen/R600/selectcc-cnde-int.ll diff --git a/test/CodeGen/R600/setcc.v4i32.ll b/test/CodeGen/R600/setcc.ll index 0752f2e63d..0752f2e63d 100644 --- a/test/CodeGen/R600/setcc.v4i32.ll +++ b/test/CodeGen/R600/setcc.ll diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll new file mode 100644 index 0000000000..6a56db352d --- /dev/null +++ b/test/CodeGen/R600/sint_to_fp.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @sint_to_fp_v4i32 +; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %value = load <4 x i32> addrspace(1) * %in + %result = sitofp <4 x i32> %value to <4 x float> + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index 4382bfff49..4d673f3ea3 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -1,11 +1,13 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s -; CHECK: @store_float +; floating-point store +; EG-CHECK: @store_f32 ; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1 +; SI-CHECK: @store_f32 ; SI-CHECK: BUFFER_STORE_DWORD -define void @store_float(float addrspace(1)* %out, float %in) { +define void @store_f32(float addrspace(1)* %out, float %in) { store float %in, float addrspace(1)* %out ret void } diff --git a/test/CodeGen/R600/store.r600.ll b/test/CodeGen/R600/store.r600.ll new file mode 100644 index 0000000000..5ffb7f1809 --- /dev/null +++ b/test/CodeGen/R600/store.r600.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s + +; XXX: Merge this test into store.ll once it is supported on SI + +; v4i32 store +; EG-CHECK: @store_v4i32 +; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 + +define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %1 = load <4 x i32> addrspace(1) * %in + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; v4f32 store +; EG-CHECK: @store_v4f32 +; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %1 = load <4 x float> addrspace(1) * %in + store <4 x float> %1, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/store.v4f32.ll b/test/CodeGen/R600/store.v4f32.ll deleted file mode 100644 index 8b0d244459..0000000000 --- a/test/CodeGen/R600/store.v4f32.ll +++ /dev/null @@ -1,9 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %1 = load <4 x float> addrspace(1) * %in - store <4 x float> %1, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/store.v4i32.ll b/test/CodeGen/R600/store.v4i32.ll deleted file mode 100644 index a659815dde..0000000000 --- a/test/CodeGen/R600/store.v4i32.ll +++ /dev/null @@ -1,9 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 - -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { - %1 = load <4 x i32> addrspace(1) * %in - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/udiv.v4i32.ll b/test/CodeGen/R600/udiv.ll index 47657a6be7..47657a6be7 100644 --- a/test/CodeGen/R600/udiv.v4i32.ll +++ b/test/CodeGen/R600/udiv.ll diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll new file mode 100644 index 0000000000..ae8fc8ed6c --- /dev/null +++ b/test/CodeGen/R600/uint_to_fp.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @uint_to_fp_v4i32 +; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %value = load <4 x i32> addrspace(1) * %in + %result = uitofp <4 x i32> %value to <4 x float> + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/urem.v4i32.ll b/test/CodeGen/R600/urem.ll index 2e7388caa6..2e7388caa6 100644 --- a/test/CodeGen/R600/urem.v4i32.ll +++ b/test/CodeGen/R600/urem.ll diff --git a/test/CodeGen/R600/vec4-expand.ll b/test/CodeGen/R600/vec4-expand.ll deleted file mode 100644 index 8f62bc6929..0000000000 --- a/test/CodeGen/R600/vec4-expand.ll +++ /dev/null @@ -1,53 +0,0 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -; CHECK: @fp_to_sint -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @fp_to_sint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %value = load <4 x float> addrspace(1) * %in - %result = fptosi <4 x float> %value to <4 x i32> - store <4 x i32> %result, <4 x i32> addrspace(1)* %out - ret void -} - -; CHECK: @fp_to_uint -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @fp_to_uint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %value = load <4 x float> addrspace(1) * %in - %result = fptoui <4 x float> %value to <4 x i32> - store <4 x i32> %result, <4 x i32> addrspace(1)* %out - ret void -} - -; CHECK: @sint_to_fp -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @sint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { - %value = load <4 x i32> addrspace(1) * %in - %result = sitofp <4 x i32> %value to <4 x float> - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} - -; CHECK: @uint_to_fp -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @uint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { - %value = load <4 x i32> addrspace(1) * %in - %result = uitofp <4 x i32> %value to <4 x float> - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} |