summaryrefslogtreecommitdiff
path: root/test/CodeGen/SystemZ/asm-11.ll
diff options
context:
space:
mode:
authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-05-06 16:17:29 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-05-06 16:17:29 +0000
commitb503b49b5105b6aad7d2a015468b84b0f64dfe8e (patch)
treea60966043fae51838cb2faa08531a7ed078e4fb6 /test/CodeGen/SystemZ/asm-11.ll
parent1d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07 (diff)
downloadllvm-b503b49b5105b6aad7d2a015468b84b0f64dfe8e.tar.gz
llvm-b503b49b5105b6aad7d2a015468b84b0f64dfe8e.tar.bz2
llvm-b503b49b5105b6aad7d2a015468b84b0f64dfe8e.tar.xz
[SystemZ] Add CodeGen test cases
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/asm-11.ll')
-rw-r--r--test/CodeGen/SystemZ/asm-11.ll41
1 files changed, 41 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/asm-11.ll b/test/CodeGen/SystemZ/asm-11.ll
new file mode 100644
index 0000000000..9bd8d7c33f
--- /dev/null
+++ b/test/CodeGen/SystemZ/asm-11.ll
@@ -0,0 +1,41 @@
+; Test the "I" constraint (8-bit unsigned constants).
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test 1 below the first valid value.
+define i32 @f1() {
+; CHECK: f1:
+; CHECK: lhi [[REG:%r[0-5]]], -1
+; CHECK: blah %r2 [[REG]]
+; CHECK: br %r14
+ %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 -1)
+ ret i32 %val
+}
+
+; Test the first valid value.
+define i32 @f2() {
+; CHECK: f2:
+; CHECK: blah %r2 0
+; CHECK: br %r14
+ %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 0)
+ ret i32 %val
+}
+
+; Test the last valid value.
+define i32 @f3() {
+; CHECK: f3:
+; CHECK: blah %r2 255
+; CHECK: br %r14
+ %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 255)
+ ret i32 %val
+}
+
+; Test 1 above the last valid value.
+define i32 @f4() {
+; CHECK: f4:
+; CHECK: lhi [[REG:%r[0-5]]], 256
+; CHECK: blah %r2 [[REG]]
+; CHECK: br %r14
+ %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 256)
+ ret i32 %val
+}