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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-05-28 10:41:11 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-05-28 10:41:11 +0000 |
commit | d50bcb2162a529534da42748ab4a418bfc9aaf06 (patch) | |
tree | fc9a388bd749853d9a65985890f9a81f37391a8b /test/CodeGen/SystemZ/branch-07.ll | |
parent | fe4716f7cf0bbabb5694fa452f435cec59bbd0e3 (diff) | |
download | llvm-d50bcb2162a529534da42748ab4a418bfc9aaf06.tar.gz llvm-d50bcb2162a529534da42748ab4a418bfc9aaf06.tar.bz2 llvm-d50bcb2162a529534da42748ab4a418bfc9aaf06.tar.xz |
[SystemZ] Register compare-and-branch support
This patch adds support for the CRJ and CGRJ instructions. Support for
the immediate forms will be a separate patch.
The architecture has a large number of comparison instructions. I think
it's generally better to concentrate on using the "best" comparison
instruction first and foremost, then only use something like CRJ if
CR really was the natual choice of comparison instruction. The patch
therefore opportunistically converts separate CR and BRC instructions
into a single CRJ while emitting instructions in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/branch-07.ll')
-rw-r--r-- | test/CodeGen/SystemZ/branch-07.ll | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/branch-07.ll b/test/CodeGen/SystemZ/branch-07.ll new file mode 100644 index 0000000000..1cab6ff28e --- /dev/null +++ b/test/CodeGen/SystemZ/branch-07.ll @@ -0,0 +1,89 @@ +; Test all condition-code masks that are relevant for CGRJ. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i64 @foo(); + +define void @f1(i64 %target) { +; CHECK: f1: +; CHECK: .cfi_def_cfa_offset +; CHECK: .L[[LABEL:.*]]: +; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]] + br label %loop +loop: + %val = call i64 @foo() + %cond = icmp eq i64 %val, %target + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f2(i64 %target) { +; CHECK: f2: +; CHECK: .cfi_def_cfa_offset +; CHECK: .L[[LABEL:.*]]: +; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]] + br label %loop +loop: + %val = call i64 @foo() + %cond = icmp ne i64 %val, %target + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f3(i64 %target) { +; CHECK: f3: +; CHECK: .cfi_def_cfa_offset +; CHECK: .L[[LABEL:.*]]: +; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]] + br label %loop +loop: + %val = call i64 @foo() + %cond = icmp sle i64 %val, %target + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f4(i64 %target) { +; CHECK: f4: +; CHECK: .cfi_def_cfa_offset +; CHECK: .L[[LABEL:.*]]: +; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]] + br label %loop +loop: + %val = call i64 @foo() + %cond = icmp slt i64 %val, %target + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f5(i64 %target) { +; CHECK: f5: +; CHECK: .cfi_def_cfa_offset +; CHECK: .L[[LABEL:.*]]: +; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]] + br label %loop +loop: + %val = call i64 @foo() + %cond = icmp sgt i64 %val, %target + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f6(i64 %target) { +; CHECK: f6: +; CHECK: .cfi_def_cfa_offset +; CHECK: .L[[LABEL:.*]]: +; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]] + br label %loop +loop: + %val = call i64 @foo() + %cond = icmp sge i64 %val, %target + br i1 %cond, label %loop, label %exit +exit: + ret void +} |