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| author | Evan Cheng <evan.cheng@apple.com> | 2012-04-27 01:27:19 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-04-27 01:27:19 +0000 |
| commit | 97a454317af1903b269d42d368d2263ab79b6ed1 (patch) | |
| tree | 4b5ddae1451e833cde36490adc81b65c00bc4fa0 /test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll | |
| parent | 97b44f9b8026fce47c1c882347f88af91c6e74c1 (diff) | |
| download | llvm-97a454317af1903b269d42d368d2263ab79b6ed1.tar.gz llvm-97a454317af1903b269d42d368d2263ab79b6ed1.tar.bz2 llvm-97a454317af1903b269d42d368d2263ab79b6ed1.tar.xz | |
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll')
| -rw-r--r-- | test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll b/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll new file mode 100644 index 0000000000..0ab5eaeefd --- /dev/null +++ b/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s +; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.) +; rdar://11331541 + +define i32 @t(i32 %a) nounwind { +; CHECK: t: +; CHECK: asrs r1, r0, #31 +; CHECK: eors r1, r0 + %tmp0 = ashr i32 %a, 31 + %tmp1 = xor i32 %tmp0, %a + ret i32 %tmp1 +} |