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| author | Jim Grosbach <grosbach@apple.com> | 2010-09-02 18:14:29 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-09-02 18:14:29 +0000 |
| commit | e7c14162631d845ff3c465bfe2c6bdf2f59dba70 (patch) | |
| tree | 2c4cebc89f1ea632c15ddd7dc0222a0c2151fd0e /test/CodeGen/Thumb2/ldr-str-imm12.ll | |
| parent | 040bbcc876c9bd2056bc73f18efaed1e1efffa0c (diff) | |
| download | llvm-e7c14162631d845ff3c465bfe2c6bdf2f59dba70.tar.gz llvm-e7c14162631d845ff3c465bfe2c6bdf2f59dba70.tar.bz2 llvm-e7c14162631d845ff3c465bfe2c6bdf2f59dba70.tar.xz | |
Now that register allocation properly considers reserved regs, simplify the
ARM register class allocation order functions to take advantage of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/ldr-str-imm12.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/ldr-str-imm12.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index 29b8e75cb8..650d788cb4 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -22,7 +22,7 @@ define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w r9, [r7, #28] +; CHECK: ldr.w {{(r[0-9])|(lr)}}, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br label %bb20 @@ -46,9 +46,9 @@ bb119: ; preds = %bb20, %bb20 bb420: ; preds = %bb20, %bb20 ; CHECK: bb420 -; CHECK: str r{{[0-7]}}, [sp] -; CHECK: str r{{[0-7]}}, [sp, #4] -; CHECK: str r{{[0-7]}}, [sp, #8] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #4] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #8] ; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24] store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 |