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| author | David Goodwin <david_goodwin@apple.com> | 2009-06-30 01:02:20 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-06-30 01:02:20 +0000 |
| commit | 4ff863c25754ef958be43a8e1d46da380c438e25 (patch) | |
| tree | e8aa0a956ac0a27d598a8079f967eda26e229af9 /test/CodeGen/Thumb2/thumb2-and.ll | |
| parent | 3fb7683bec8c8edb24e80c95f3b0668c6ecc0ae6 (diff) | |
| download | llvm-4ff863c25754ef958be43a8e1d46da380c438e25.tar.gz llvm-4ff863c25754ef958be43a8e1d46da380c438e25.tar.bz2 llvm-4ff863c25754ef958be43a8e1d46da380c438e25.tar.xz | |
Enhance tests to include shifted-register operand testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74490 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/thumb2-and.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-and.ll | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/test/CodeGen/Thumb2/thumb2-and.ll b/test/CodeGen/Thumb2/thumb2-and.ll index 360c977f45..ab191d5684 100644 --- a/test/CodeGen/Thumb2/thumb2-and.ll +++ b/test/CodeGen/Thumb2/thumb2-and.ll @@ -1,6 +1,36 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a, i32 %b) { %tmp = and i32 %a, %b ret i32 %tmp } + +define i32 @f2(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f3(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f5(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} |