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| author | Edward O'Callaghan <eocallaghan@auroraux.org> | 2009-11-22 15:35:28 +0000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@auroraux.org> | 2009-11-22 15:35:28 +0000 |
| commit | 18d18b71d5955274b95ac96cbb8353b4766d1995 (patch) | |
| tree | 6fc1c076bb29044c563077cca210ab06664c21a5 /test/CodeGen/Thumb2/thumb2-orn.ll | |
| parent | f4a93dd70e5f43e54366e184cf8eea8b783a05f8 (diff) | |
| download | llvm-18d18b71d5955274b95ac96cbb8353b4766d1995.tar.gz llvm-18d18b71d5955274b95ac96cbb8353b4766d1995.tar.bz2 llvm-18d18b71d5955274b95ac96cbb8353b4766d1995.tar.xz | |
Miss two, PR5307.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89596 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/thumb2-orn.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-orn.ll | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/test/CodeGen/Thumb2/thumb2-orn.ll b/test/CodeGen/Thumb2/thumb2-orn.ll index d4222c2b2d..97a3fd75f0 100644 --- a/test/CodeGen/Thumb2/thumb2-orn.ll +++ b/test/CodeGen/Thumb2/thumb2-orn.ll @@ -1,32 +1,37 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = or i32 %a, %tmp ret i32 %tmp1 } +; CHECK: f1: +; CHECK: orn r0, r0, r1 define i32 @f2(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = or i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f2: +; CHECK: orn r0, r0, r1 define i32 @f3(i32 %a, i32 %b) { %tmp = xor i32 4294967295, %b %tmp1 = or i32 %a, %tmp ret i32 %tmp1 } +; CHECK: f3: +; CHECK: orn r0, r0, r1 define i32 @f4(i32 %a, i32 %b) { %tmp = xor i32 4294967295, %b %tmp1 = or i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f4: +; CHECK: orn r0, r0, r1 define i32 @f5(i32 %a, i32 %b) { %tmp = shl i32 %b, 5 @@ -34,6 +39,8 @@ define i32 @f5(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f5: +; CHECK: orn r0, r0, r1, lsl #5 define i32 @f6(i32 %a, i32 %b) { %tmp = lshr i32 %b, 6 @@ -41,6 +48,8 @@ define i32 @f6(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f6: +; CHECK: orn r0, r0, r1, lsr #6 define i32 @f7(i32 %a, i32 %b) { %tmp = ashr i32 %b, 7 @@ -48,6 +57,8 @@ define i32 @f7(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f7: +; CHECK: orn r0, r0, r1, asr #7 define i32 @f8(i32 %a, i32 %b) { %l8 = shl i32 %a, 24 @@ -57,3 +68,5 @@ define i32 @f8(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f8: +; CHECK: orn r0, r0, r0, ror #8 |