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| author | Evan Cheng <evan.cheng@apple.com> | 2009-08-10 23:56:04 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-10 23:56:04 +0000 |
| commit | 3a1f0f6785e27eb8ede455a3583ca8c885d3911e (patch) | |
| tree | ee8d3a8569c2ef730e5c38c03272af07580a08a3 /test/CodeGen/Thumb2/thumb2-orr.ll | |
| parent | 52c1afcaea61440950a11a4ccadac4354420d727 (diff) | |
| download | llvm-3a1f0f6785e27eb8ede455a3583ca8c885d3911e.tar.gz llvm-3a1f0f6785e27eb8ede455a3583ca8c885d3911e.tar.bz2 llvm-3a1f0f6785e27eb8ede455a3583ca8c885d3911e.tar.xz | |
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78622 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/thumb2-orr.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-orr.ll | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/test/CodeGen/Thumb2/thumb2-orr.ll b/test/CodeGen/Thumb2/thumb2-orr.ll index 22b34798d4..221991ef3d 100644 --- a/test/CodeGen/Thumb2/thumb2-orr.ll +++ b/test/CodeGen/Thumb2/thumb2-orr.ll @@ -1,33 +1,39 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\.w\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 1 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: orrs r0, r1 %tmp2 = or i32 %a, %b ret i32 %tmp2 } define i32 @f5(i32 %a, i32 %b) { +; CHECK: f5: +; CHECK: orr.w r0, r0, r1, lsl #5 %tmp = shl i32 %b, 5 %tmp2 = or i32 %a, %tmp ret i32 %tmp2 } define i32 @f6(i32 %a, i32 %b) { +; CHECK: f6: +; CHECK: orr.w r0, r0, r1, lsr #6 %tmp = lshr i32 %b, 6 %tmp2 = or i32 %a, %tmp ret i32 %tmp2 } define i32 @f7(i32 %a, i32 %b) { +; CHECK: f7: +; CHECK: orr.w r0, r0, r1, asr #7 %tmp = ashr i32 %b, 7 %tmp2 = or i32 %a, %tmp ret i32 %tmp2 } define i32 @f8(i32 %a, i32 %b) { +; CHECK: f8: +; CHECK: orr.w r0, r0, r0, ror #8 %l8 = shl i32 %a, 24 %r8 = lshr i32 %a, 8 %tmp = or i32 %l8, %r8 |