diff options
author | Chris Lattner <sabre@nondot.org> | 2010-10-08 03:57:25 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2010-10-08 03:57:25 +0000 |
commit | 15df55d8c238ddd4b595dc0d762fe4c391352f11 (patch) | |
tree | 5d469a4ba52cf55dba02d56b1f8a7f4ee9e43e86 /test/CodeGen/X86/3addr-or.ll | |
parent | 99ae6659daaebeb32df91653fad09748fda8bcb2 (diff) | |
download | llvm-15df55d8c238ddd4b595dc0d762fe4c391352f11.tar.gz llvm-15df55d8c238ddd4b595dc0d762fe4c391352f11.tar.bz2 llvm-15df55d8c238ddd4b595dc0d762fe4c391352f11.tar.xz |
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/3addr-or.ll')
-rw-r--r-- | test/CodeGen/X86/3addr-or.ll | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/test/CodeGen/X86/3addr-or.ll b/test/CodeGen/X86/3addr-or.ll index 30a1f36850..912bdc2154 100644 --- a/test/CodeGen/X86/3addr-or.ll +++ b/test/CodeGen/X86/3addr-or.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; rdar://7527734 -define i32 @test(i32 %x) nounwind readnone ssp { +define i32 @test1(i32 %x) nounwind readnone ssp { entry: -; CHECK: test: +; CHECK: test1: ; CHECK: leal 3(%rdi), %eax %0 = shl i32 %x, 5 ; <i32> [#uses=1] %1 = or i32 %0, 3 ; <i32> [#uses=1] @@ -25,3 +25,37 @@ define i64 @test2(i8 %A, i8 %B) nounwind { %H = or i64 %G, %E ; <i64> [#uses=1] ret i64 %H } + +;; Test that OR is only emitted as LEA, not as ADD. + +define void @test3(i32 %x, i32* %P) nounwind readnone ssp { +entry: +; No reason to emit an add here, should be an or. +; CHECK: test3: +; CHECK: orl $3, %edi + %0 = shl i32 %x, 5 + %1 = or i32 %0, 3 + store i32 %1, i32* %P + ret void +} + +define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp { +entry: + %and = and i32 %a, 6 + %and2 = and i32 %b, 16 + %or = or i32 %and2, %and + ret i32 %or +; CHECK: test4: +; CHECK: leal (%rsi,%rdi), %eax +} + +define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp { +entry: + %and = and i32 %a, 6 + %and2 = and i32 %b, 16 + %or = or i32 %and2, %and + store i32 %or, i32* %P, align 4 + ret void +; CHECK: test5: +; CHECK: orl +} |