diff options
author | Daniel Dunbar <daniel@zuster.org> | 2010-10-08 02:07:26 +0000 |
---|---|---|
committer | Daniel Dunbar <daniel@zuster.org> | 2010-10-08 02:07:26 +0000 |
commit | 32f0cdba302d5f48401aadb9a2eb9e3efd9e6833 (patch) | |
tree | c5f70d2d6eddb0b755fe6aac34964f161ed6c8bd /test/CodeGen/X86/3addr-or.ll | |
parent | 6aa526bf76ba74b79ebf4d96d2c1f12d59067530 (diff) | |
download | llvm-32f0cdba302d5f48401aadb9a2eb9e3efd9e6833.tar.gz llvm-32f0cdba302d5f48401aadb9a2eb9e3efd9e6833.tar.bz2 llvm-32f0cdba302d5f48401aadb9a2eb9e3efd9e6833.tar.xz |
Revert "reimplement the second half of the or/add optimization. We should now",
which depends on r116007, which I am about to revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/3addr-or.ll')
-rw-r--r-- | test/CodeGen/X86/3addr-or.ll | 38 |
1 files changed, 2 insertions, 36 deletions
diff --git a/test/CodeGen/X86/3addr-or.ll b/test/CodeGen/X86/3addr-or.ll index 912bdc2154..30a1f36850 100644 --- a/test/CodeGen/X86/3addr-or.ll +++ b/test/CodeGen/X86/3addr-or.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; rdar://7527734 -define i32 @test1(i32 %x) nounwind readnone ssp { +define i32 @test(i32 %x) nounwind readnone ssp { entry: -; CHECK: test1: +; CHECK: test: ; CHECK: leal 3(%rdi), %eax %0 = shl i32 %x, 5 ; <i32> [#uses=1] %1 = or i32 %0, 3 ; <i32> [#uses=1] @@ -25,37 +25,3 @@ define i64 @test2(i8 %A, i8 %B) nounwind { %H = or i64 %G, %E ; <i64> [#uses=1] ret i64 %H } - -;; Test that OR is only emitted as LEA, not as ADD. - -define void @test3(i32 %x, i32* %P) nounwind readnone ssp { -entry: -; No reason to emit an add here, should be an or. -; CHECK: test3: -; CHECK: orl $3, %edi - %0 = shl i32 %x, 5 - %1 = or i32 %0, 3 - store i32 %1, i32* %P - ret void -} - -define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp { -entry: - %and = and i32 %a, 6 - %and2 = and i32 %b, 16 - %or = or i32 %and2, %and - ret i32 %or -; CHECK: test4: -; CHECK: leal (%rsi,%rdi), %eax -} - -define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp { -entry: - %and = and i32 %a, 6 - %and2 = and i32 %b, 16 - %or = or i32 %and2, %and - store i32 %or, i32* %P, align 4 - ret void -; CHECK: test5: -; CHECK: orl -} |