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| author | Eli Friedman <eli.friedman@gmail.com> | 2012-06-25 23:42:33 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2012-06-25 23:42:33 +0000 |
| commit | 52d418df5d67ffdf4c9782c5fa8d3fdbd2478631 (patch) | |
| tree | 01be5d4e040d5946a893efac8f823dab3a40681e /test/CodeGen/X86/asm-reg-type-mismatch.ll | |
| parent | fd99cabdc6de1eadda0e9a45d0acc8aa7c2f8f67 (diff) | |
| download | llvm-52d418df5d67ffdf4c9782c5fa8d3fdbd2478631.tar.gz llvm-52d418df5d67ffdf4c9782c5fa8d3fdbd2478631.tar.bz2 llvm-52d418df5d67ffdf4c9782c5fa8d3fdbd2478631.tar.xz | |
Make some ugly hacks for inline asm operands which name a specific register a bit more thorough. PR13196.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159176 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/asm-reg-type-mismatch.ll')
| -rw-r--r-- | test/CodeGen/X86/asm-reg-type-mismatch.ll | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/test/CodeGen/X86/asm-reg-type-mismatch.ll b/test/CodeGen/X86/asm-reg-type-mismatch.ll new file mode 100644 index 0000000000..47accdbc07 --- /dev/null +++ b/test/CodeGen/X86/asm-reg-type-mismatch.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mcpu=core2 | FileCheck %s +; PR2715 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + %struct.XPTTypeDescriptorPrefix = type { i8 } + %struct.nsISupports = type { i32 (...)** } + %struct.nsXPTCMiniVariant = type { %"struct.nsXPTCMiniVariant::._39" } + %"struct.nsXPTCMiniVariant::._39" = type { i64 } + %struct.nsXPTCVariant = type { %struct.nsXPTCMiniVariant, i8*, %struct.nsXPTType, i8 } + %struct.nsXPTType = type { %struct.XPTTypeDescriptorPrefix } + +define i32 @test1(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind { +entry: + call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},~{dirflag},~{fpsr},~{flags}"( double undef, double undef, double undef, double 1.0, double undef, double 0.0, double undef, double 0.0 ) nounwind + ret i32 0 + ; CHECK: test1 + ; CHECK-NOT: movap + ; CHECK: xorps + ; CHECK: xorps + ; CHECK-NOT: movap +} + +define i64 @test2() nounwind { +entry: + %0 = tail call i64 asm sideeffect "movq $1, $0", "={xmm7},*m,~{dirflag},~{fpsr},~{flags}"(i64* null) nounwind + ret i64 %0 + ; CHECK: test2 + ; CHECK: movq {{.*}}, %xmm7 + ; CHECK: movd %xmm7, %rax +} |