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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2012-04-27 12:07:43 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2012-04-27 12:07:43 +0000 |
| commit | 17c836c4b51a14f07a5d5442cf2e984474a8f57d (patch) | |
| tree | 74181d3329eae68c0137d0d18c5ce2db3ff901fe /test/CodeGen/X86/fp-stack-compare.ll | |
| parent | c84f975e6fa65049ecd3268f830218e791893efd (diff) | |
| download | llvm-17c836c4b51a14f07a5d5442cf2e984474a8f57d.tar.gz llvm-17c836c4b51a14f07a5d5442cf2e984474a8f57d.tar.bz2 llvm-17c836c4b51a14f07a5d5442cf2e984474a8f57d.tar.xz | |
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/fp-stack-compare.ll')
| -rw-r--r-- | test/CodeGen/X86/fp-stack-compare.ll | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/test/CodeGen/X86/fp-stack-compare.ll b/test/CodeGen/X86/fp-stack-compare.ll index f3998b67f6..a8557adeaf 100644 --- a/test/CodeGen/X86/fp-stack-compare.ll +++ b/test/CodeGen/X86/fp-stack-compare.ll @@ -1,8 +1,11 @@ ; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s -; PR1012 +; PR6679 define float @foo(float* %col.2.0) { -; CHECK: fucompi +; CHECK: fucomp +; CHECK-NOT: fucompi +; CHECK: j +; CHECK-NOT: fcmov %tmp = load float* %col.2.0 %tmp16 = fcmp olt float %tmp, 0.000000e+00 %tmp20 = fsub float -0.000000e+00, %tmp |