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author | Dan Gohman <gohman@apple.com> | 2009-04-14 22:17:14 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-04-14 22:17:14 +0000 |
commit | 5ec3b427c850d8c61aaa29e3421019bdff9b77f1 (patch) | |
tree | 6ab829b839dc3b0819536ed10a746055818457dc /test/CodeGen/X86/h-registers-0.ll | |
parent | 0526653956e924304f4c56ff87f72cecbb49fba2 (diff) | |
download | llvm-5ec3b427c850d8c61aaa29e3421019bdff9b77f1.tar.gz llvm-5ec3b427c850d8c61aaa29e3421019bdff9b77f1.tar.bz2 llvm-5ec3b427c850d8c61aaa29e3421019bdff9b77f1.tar.xz |
When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REG
operator is used by a CopyToReg to export the value to a different
block, don't reuse the CopyToReg's register for the subreg operation
result if the register isn't precisely the right class for the
subreg operation.
Also, rename the h-registers.ll test, now that there are more
than one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69087 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/h-registers-0.ll')
-rw-r--r-- | test/CodeGen/X86/h-registers-0.ll | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll new file mode 100644 index 0000000000..2777be9cc3 --- /dev/null +++ b/test/CodeGen/X86/h-registers-0.ll @@ -0,0 +1,48 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4 +; RUN: llvm-as < %s | llc -march=x86 > %t +; RUN: grep {incb %ah} %t | count 3 +; RUN: grep {movzbl %ah,} %t | count 3 + +; Use h registers. On x86-64, codegen doesn't support general allocation +; of h registers yet, due to x86 encoding complications. + +define void @bar64(i64 inreg %x, i8* inreg %p) nounwind { + %t0 = lshr i64 %x, 8 + %t1 = trunc i64 %t0 to i8 + %t2 = add i8 %t1, 1 + store i8 %t2, i8* %p + ret void +} + +define void @bar32(i32 inreg %x, i8* inreg %p) nounwind { + %t0 = lshr i32 %x, 8 + %t1 = trunc i32 %t0 to i8 + %t2 = add i8 %t1, 1 + store i8 %t2, i8* %p + ret void +} + +define void @bar16(i16 inreg %x, i8* inreg %p) nounwind { + %t0 = lshr i16 %x, 8 + %t1 = trunc i16 %t0 to i8 + %t2 = add i8 %t1, 1 + store i8 %t2, i8* %p + ret void +} + +define i64 @qux64(i64 inreg %x) nounwind { + %t0 = lshr i64 %x, 8 + %t1 = and i64 %t0, 255 + ret i64 %t1 +} + +define i32 @qux32(i32 inreg %x) nounwind { + %t0 = lshr i32 %x, 8 + %t1 = and i32 %t0, 255 + ret i32 %t1 +} + +define i16 @qux16(i16 inreg %x) nounwind { + %t0 = lshr i16 %x, 8 + ret i16 %t0 +} |