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| author | Evan Cheng <evan.cheng@apple.com> | 2011-11-10 07:43:16 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-11-10 07:43:16 +0000 |
| commit | 623a7e146bd86747dc46a6f8bb9993fc217d6b78 (patch) | |
| tree | 72b44ba84e3cb347279c411ac8b159e6fecaf9b0 /test/CodeGen/X86/lsr-reuse-trunc.ll | |
| parent | 4dbe96e22ff4989577cf4854f717b9d972094f87 (diff) | |
| download | llvm-623a7e146bd86747dc46a6f8bb9993fc217d6b78.tar.gz llvm-623a7e146bd86747dc46a6f8bb9993fc217d6b78.tar.bz2 llvm-623a7e146bd86747dc46a6f8bb9993fc217d6b78.tar.xz | |
Use a bigger hammer to fix PR11314 by disabling the "forcing two-address
instruction lower optimization" in the pre-RA scheduler.
The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.
Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144267 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/lsr-reuse-trunc.ll')
| -rw-r--r-- | test/CodeGen/X86/lsr-reuse-trunc.ll | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll index 1f87089f80..5f5e0937a3 100644 --- a/test/CodeGen/X86/lsr-reuse-trunc.ll +++ b/test/CodeGen/X86/lsr-reuse-trunc.ll @@ -4,13 +4,14 @@ ; Full strength reduction wouldn't reduce register pressure, so LSR should ; stick with indexing here. +; FIXME: This is worse off from disabling of scheduler 2-address hack. ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] +; CHECK: leaq 4(%rax), %{{rcx|r9}} ; CHECK: cvtdq2ps ; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]] ; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4) -; CHECK: addq $4, %rax -; CHECK: cmpl %eax, (%{{rdx|r8}}) -; CHECK-NEXT: jg +; CHECK: cmpl %{{ecx|r9d}}, (%{{rdx|r8}}) +; CHECK: jg define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind { entry: |