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authorQuentin Colombet <qcolombet@apple.com>2013-05-31 17:20:29 +0000
committerQuentin Colombet <qcolombet@apple.com>2013-05-31 17:20:29 +0000
commit5b00f4edcbebad3b5474e3052b6d30ceb5d68e88 (patch)
tree25e7625de4948f18d1b1ec8d0584b674f185b52b /test/CodeGen/X86/masked-iv-safe.ll
parentbed23081860275c79137f65d592920e7991b8198 (diff)
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Modify how the formulae are rated in Loop Strength Reduce.
Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/masked-iv-safe.ll')
-rw-r--r--test/CodeGen/X86/masked-iv-safe.ll5
1 files changed, 2 insertions, 3 deletions
diff --git a/test/CodeGen/X86/masked-iv-safe.ll b/test/CodeGen/X86/masked-iv-safe.ll
index a7b036e9b6..c33cac2e05 100644
--- a/test/CodeGen/X86/masked-iv-safe.ll
+++ b/test/CodeGen/X86/masked-iv-safe.ll
@@ -3,9 +3,8 @@
; RUN: not grep movz %t
; RUN: not grep sar %t
; RUN: not grep shl %t
-; RUN: grep add %t | count 1
-; RUN: grep inc %t | count 4
-; RUN: grep dec %t | count 2
+; RUN: grep add %t | count 5
+; RUN: grep inc %t | count 2
; RUN: grep lea %t | count 3
; Optimize away zext-inreg and sext-inreg on the loop induction