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authorEric Christopher <echristo@apple.com>2011-07-08 00:04:56 +0000
committerEric Christopher <echristo@apple.com>2011-07-08 00:04:56 +0000
commit77ed1353bfd456efd35c2b6e17115ce624d19e92 (patch)
treeb554de3a2d03d904df62e860a852102cfae179f8 /test/CodeGen/X86/membarrier.ll
parent794bf17cbe0bac301ef9e52fb4a0295bfdfe0cab (diff)
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Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine. Fixes PR9675 and rdar://9740801 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/membarrier.ll')
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diff --git a/test/CodeGen/X86/membarrier.ll b/test/CodeGen/X86/membarrier.ll
new file mode 100644
index 0000000000..42f8ef5ff0
--- /dev/null
+++ b/test/CodeGen/X86/membarrier.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 -mattr=-sse -O0
+; PR9675
+
+define i32 @t() {
+entry:
+ %i = alloca i32, align 4
+ store i32 1, i32* %i, align 4
+ call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+ %0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1)
+ call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+ ret i32 0
+}
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind