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| author | Andrew Trick <atrick@apple.com> | 2012-12-05 21:37:42 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-12-05 21:37:42 +0000 |
| commit | 553c42cefc9abe1f10ee33d34a12498b8ac12fe6 (patch) | |
| tree | b9be40e319a9d3817a9913cf982b108391d7fc48 /test/CodeGen/X86/misched-new.ll | |
| parent | 0602bb46596485b43fa8b86abbc8485d502025ce (diff) | |
| download | llvm-553c42cefc9abe1f10ee33d34a12498b8ac12fe6.tar.gz llvm-553c42cefc9abe1f10ee33d34a12498b8ac12fe6.tar.bz2 llvm-553c42cefc9abe1f10ee33d34a12498b8ac12fe6.tar.xz | |
RegisterPresssureTracker: Track live physical register by unit.
This is much simpler to reason about, more efficient, and
fixes some corner cases involving implicit super-register defs.
Fixed rdar://12797931.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169425 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/misched-new.ll')
| -rw-r--r-- | test/CodeGen/X86/misched-new.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/X86/misched-new.ll b/test/CodeGen/X86/misched-new.ll index a39ea03af5..89e45b7cfc 100644 --- a/test/CodeGen/X86/misched-new.ll +++ b/test/CodeGen/X86/misched-new.ll @@ -1,6 +1,9 @@ ; RUN: llc < %s -march=x86-64 -mcpu=core2 -x86-early-ifcvt -enable-misched \ ; RUN: -misched=shuffle -misched-bottomup -verify-machineinstrs \ ; RUN: | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=core2 -x86-early-ifcvt -enable-misched \ +; RUN: -misched=shuffle -misched-topdown -verify-machineinstrs \ +; RUN: | FileCheck %s --check-prefix TOPDOWN ; REQUIRES: asserts ; ; Interesting MachineScheduler cases. @@ -77,3 +80,30 @@ define void @hasundef() unnamed_addr uwtable ssp align 2 { ; <label>:5 ; preds = %3 ret void } + +; Test top-down subregister liveness tracking. Self-verification +; catches any pressure set underflow. +; rdar://12797931. +; +; TOPDOWN: @testSubregTracking +; TOPDOWN: divb +; TOPDOWN: movzbl %al +; TOPDOWN: ret +define void @testSubregTracking() nounwind uwtable ssp align 2 { + %tmp = load i8* undef, align 1 + %tmp6 = sub i8 0, %tmp + %tmp7 = load i8* undef, align 1 + %tmp8 = udiv i8 %tmp6, %tmp7 + %tmp9 = zext i8 %tmp8 to i64 + %tmp10 = load i8* undef, align 1 + %tmp11 = zext i8 %tmp10 to i64 + %tmp12 = mul i64 %tmp11, %tmp9 + %tmp13 = urem i8 %tmp6, %tmp7 + %tmp14 = zext i8 %tmp13 to i32 + %tmp15 = add nsw i32 %tmp14, 0 + %tmp16 = add i32 %tmp15, 0 + store i32 %tmp16, i32* undef, align 4 + %tmp17 = add i64 0, %tmp12 + store i64 %tmp17, i64* undef, align 8 + ret void +} |