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author | Duncan Sands <baldrick@free.fr> | 2011-09-17 16:49:39 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2011-09-17 16:49:39 +0000 |
commit | 6bcd2196e5febb97efe188d0d6de403c577d96fc (patch) | |
tree | b147a99b1f7f3b65365ba8535f8466ab53f5d766 /test/CodeGen/X86/sse-minmax.ll | |
parent | 2c693dc1261d8b8d92b5c96cf00ec873dde86bb2 (diff) | |
download | llvm-6bcd2196e5febb97efe188d0d6de403c577d96fc.tar.gz llvm-6bcd2196e5febb97efe188d0d6de403c577d96fc.tar.bz2 llvm-6bcd2196e5febb97efe188d0d6de403c577d96fc.tar.xz |
Synthesize x86 max/min instructions also for vectors (i.e. produce
maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/sse-minmax.ll')
-rw-r--r-- | test/CodeGen/X86/sse-minmax.ll | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll index ff0af25ce2..af1a73b8f1 100644 --- a/test/CodeGen/X86/sse-minmax.ll +++ b/test/CodeGen/X86/sse-minmax.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs | FileCheck %s -; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s -; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -promote-elements | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=UNSAFE %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=FINITE %s ; Some of these patterns can be matched as SSE min or max. Some of ; then can be matched provided that the operands are swapped. @@ -933,3 +933,35 @@ entry: %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1] ret double %x_addr.0 } + +; UNSAFE: maxpd: +; UNSAFE: maxpd +define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) { + %max_is_x = fcmp oge <2 x double> %x, %y + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %max +} + +; UNSAFE: minpd: +; UNSAFE: minpd +define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) { + %min_is_x = fcmp ole <2 x double> %x, %y + %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %min +} + +; UNSAFE: maxps: +; UNSAFE: maxps +define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) { + %max_is_x = fcmp oge <4 x float> %x, %y + %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y + ret <4 x float> %max +} + +; UNSAFE: minps: +; UNSAFE: minps +define <4 x float> @minps(<4 x float> %x, <4 x float> %y) { + %min_is_x = fcmp ole <4 x float> %x, %y + %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y + ret <4 x float> %min +} |