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| author | Andrew Trick <atrick@apple.com> | 2013-06-24 09:13:20 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-06-24 09:13:20 +0000 |
| commit | 98a9b72e8c56dc13a2617de84503a3d78352789c (patch) | |
| tree | fd31bd17c5362627889925766aad73d8cdaddb32 /test/CodeGen/X86/store-narrow.ll | |
| parent | 4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1 (diff) | |
| download | llvm-98a9b72e8c56dc13a2617de84503a3d78352789c.tar.gz llvm-98a9b72e8c56dc13a2617de84503a3d78352789c.tar.bz2 llvm-98a9b72e8c56dc13a2617de84503a3d78352789c.tar.xz | |
Temporarily enable MI-Sched on X86.
Sorry for the unit test churn. I'll try to make the change permanently
next time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/store-narrow.ll')
| -rw-r--r-- | test/CodeGen/X86/store-narrow.ll | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll index 0dd228eb14..7855a4c5b3 100644 --- a/test/CodeGen/X86/store-narrow.ll +++ b/test/CodeGen/X86/store-narrow.ll @@ -12,7 +12,7 @@ entry: %D = or i32 %C, %B store i32 %D, i32* %a0, align 4 ret void - + ; X64: test1: ; X64: movb %sil, (%rdi) @@ -34,8 +34,8 @@ entry: ; X64: movb %sil, 1(%rdi) ; X32: test2: -; X32: movb 8(%esp), %al -; X32: movb %al, 1(%{{.*}}) +; X32: movb 8(%esp), %[[REG:[abcd]l]] +; X32: movb %[[REG]], 1(%{{.*}}) } define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp { @@ -67,8 +67,8 @@ entry: ; X64: movw %si, 2(%rdi) ; X32: test4: -; X32: movl 8(%esp), %eax -; X32: movw %ax, 2(%{{.*}}) +; X32: movl 8(%esp), %e[[REG:[abcd]x]] +; X32: movw %[[REG]], 2(%{{.*}}) } define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp { @@ -84,8 +84,8 @@ entry: ; X64: movw %si, 2(%rdi) ; X32: test5: -; X32: movzwl 8(%esp), %eax -; X32: movw %ax, 2(%{{.*}}) +; X32: movzwl 8(%esp), %e[[REG:[abcd]x]] +; X32: movw %[[REG]], 2(%{{.*}}) } define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp { @@ -102,8 +102,8 @@ entry: ; X32: test6: -; X32: movb 8(%esp), %al -; X32: movb %al, 5(%{{.*}}) +; X32: movb 8(%esp), %[[REG:[abcd]l]] +; X32: movb %[[REG]], 5(%{{.*}}) } define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind { @@ -121,8 +121,8 @@ entry: ; X32: test7: -; X32: movb 8(%esp), %cl -; X32: movb %cl, 5(%{{.*}}) +; X32: movb 8(%esp), %[[REG:[abcd]l]] +; X32: movb %[[REG]], 5(%{{.*}}) } ; PR7833 |