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authorNadav Rotem <nadav.rotem@intel.com>2011-10-16 20:31:33 +0000
committerNadav Rotem <nadav.rotem@intel.com>2011-10-16 20:31:33 +0000
commit8fb06b3e8f7fc92e472e17fecf5ee3ba44fbb6ab (patch)
tree0bb4f05809105f8db17e8f199f0627d92cd6f04c /test/CodeGen/X86/widen_arith-1.ll
parentc4a90c5271de99e682b00986c9ca7cde3e1dde4f (diff)
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Enable element promotion type legalization by deafault.
Changed tests which assumed that vectors are legalized by widening them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/widen_arith-1.ll')
-rw-r--r--test/CodeGen/X86/widen_arith-1.ll6
1 files changed, 2 insertions, 4 deletions
diff --git a/test/CodeGen/X86/widen_arith-1.ll b/test/CodeGen/X86/widen_arith-1.ll
index 4b8016dc71..85367e85f4 100644
--- a/test/CodeGen/X86/widen_arith-1.ll
+++ b/test/CodeGen/X86/widen_arith-1.ll
@@ -1,12 +1,10 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
-; Widen a v3i8 to v16i8 to use a vector add
-
define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind {
entry:
; CHECK-NOT: pextrw
-; CHECK: paddb
-; CHECK: pextrb
+; CHECK: add
+
%dst.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2]
%src.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2]
%n.addr = alloca i32 ; <i32*> [#uses=2]