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authorEvan Cheng <evan.cheng@apple.com>2010-01-11 22:03:29 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-01-11 22:03:29 +0000
commit199c4240feedec2f9dbd0d4c4c0a32fa46e50270 (patch)
tree23f814b690f461e89f44e4455bdfce90fafb6493 /test/CodeGen/X86
parentc31b0fc31f69435eeb6cd456158239e275f52f31 (diff)
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Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93191 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
-rw-r--r--test/CodeGen/X86/3addr-or.ll16
-rw-r--r--test/CodeGen/X86/fast-isel.ll2
2 files changed, 17 insertions, 1 deletions
diff --git a/test/CodeGen/X86/3addr-or.ll b/test/CodeGen/X86/3addr-or.ll
index 395ba46aab..30a1f36850 100644
--- a/test/CodeGen/X86/3addr-or.ll
+++ b/test/CodeGen/X86/3addr-or.ll
@@ -9,3 +9,19 @@ entry:
%1 = or i32 %0, 3 ; <i32> [#uses=1]
ret i32 %1
}
+
+define i64 @test2(i8 %A, i8 %B) nounwind {
+; CHECK: test2:
+; CHECK: shrq $4
+; CHECK-NOT: movq
+; CHECK-NOT: orq
+; CHECK: leaq
+; CHECK: ret
+ %C = zext i8 %A to i64 ; <i64> [#uses=1]
+ %D = shl i64 %C, 4 ; <i64> [#uses=1]
+ %E = and i64 %D, 48 ; <i64> [#uses=1]
+ %F = zext i8 %B to i64 ; <i64> [#uses=1]
+ %G = lshr i64 %F, 4 ; <i64> [#uses=1]
+ %H = or i64 %G, %E ; <i64> [#uses=1]
+ ret i64 %H
+}
diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll
index 3dcd736a14..84b3fd7caf 100644
--- a/test/CodeGen/X86/fast-isel.ll
+++ b/test/CodeGen/X86/fast-isel.ll
@@ -14,7 +14,7 @@ fast:
%t1 = mul i32 %t0, %s
%t2 = sub i32 %t1, %s
%t3 = and i32 %t2, %s
- %t4 = or i32 %t3, %s
+ %t4 = xor i32 %t3, 3
%t5 = xor i32 %t4, %s
%t6 = add i32 %t5, 2
%t7 = getelementptr i32* %y, i32 1