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| author | Evan Cheng <evan.cheng@apple.com> | 2008-05-04 09:15:50 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-05-04 09:15:50 +0000 |
| commit | 5759f97f50b49aed2f7763133a4af3aa54e24c5a (patch) | |
| tree | 031122becbc447799e4ea07d18c0b29a7071c45a /test/CodeGen/X86 | |
| parent | 529bd53411c6f583fd8ed435adf4c0f923d185fd (diff) | |
| download | llvm-5759f97f50b49aed2f7763133a4af3aa54e24c5a.tar.gz llvm-5759f97f50b49aed2f7763133a4af3aa54e24c5a.tar.bz2 llvm-5759f97f50b49aed2f7763133a4af3aa54e24c5a.tar.xz | |
Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
| -rw-r--r-- | test/CodeGen/X86/mmx-shift.ll | 11 | ||||
| -rw-r--r-- | test/CodeGen/X86/vec_shift3.ll | 26 |
2 files changed, 37 insertions, 0 deletions
diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll index 82eeafd075..277cf075cb 100644 --- a/test/CodeGen/X86/mmx-shift.ll +++ b/test/CodeGen/X86/mmx-shift.ll @@ -1,6 +1,7 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psllq | grep 32 ; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psllq | grep 32 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psrad +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psrlw define i64 @t1(<1 x i64> %mm1) nounwind { entry: @@ -19,3 +20,13 @@ entry: } declare <2 x i32> @llvm.x86.mmx.psra.d(<2 x i32>, <2 x i32>) nounwind readnone + +define i64 @t3(<1 x i64> %mm1, i32 %bits) nounwind { +entry: + %tmp6 = bitcast <1 x i64> %mm1 to <4 x i16> ; <<4 x i16>> [#uses=1] + %tmp8 = tail call <4 x i16> @llvm.x86.mmx.psrli.w( <4 x i16> %tmp6, i32 %bits ) nounwind readnone ; <<4 x i16>> [#uses=1] + %retval1314 = bitcast <4 x i16> %tmp8 to i64 ; <i64> [#uses=1] + ret i64 %retval1314 +} + +declare <4 x i16> @llvm.x86.mmx.psrli.w(<4 x i16>, i32) nounwind readnone diff --git a/test/CodeGen/X86/vec_shift3.ll b/test/CodeGen/X86/vec_shift3.ll new file mode 100644 index 0000000000..2641c5d596 --- /dev/null +++ b/test/CodeGen/X86/vec_shift3.ll @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psllq +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psraw +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movd | count 2 + +define <2 x i64> @t1(<2 x i64> %x1, i32 %bits) nounwind { +entry: + %tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 %bits ) nounwind readnone ; <<2 x i64>> [#uses=1] + ret <2 x i64> %tmp3 +} + +define <2 x i64> @t2(<2 x i64> %x1) nounwind { +entry: + %tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; <<2 x i64>> [#uses=1] + ret <2 x i64> %tmp3 +} + +define <2 x i64> @t3(<2 x i64> %x1, i32 %bits) nounwind { +entry: + %tmp2 = bitcast <2 x i64> %x1 to <8 x i16> ; <<8 x i16>> [#uses=1] + %tmp4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w( <8 x i16> %tmp2, i32 %bits ) nounwind readnone ; <<8 x i16>> [#uses=1] + %tmp5 = bitcast <8 x i16> %tmp4 to <2 x i64> ; <<2 x i64>> [#uses=1] + ret <2 x i64> %tmp5 +} + +declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone +declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone |