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author | Chris Lattner <sabre@nondot.org> | 2010-12-19 22:08:31 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-12-19 22:08:31 +0000 |
commit | c19d1c3ba2b216f0f91d71cf6fc2e983fc995854 (patch) | |
tree | bac5a92aeaf2d30963e52aa20486d19a0fef1b06 /test/CodeGen/X86 | |
parent | 22d67cf6ac84c06867681a2fe72f78d5d2b9444d (diff) | |
download | llvm-c19d1c3ba2b216f0f91d71cf6fc2e983fc995854.tar.gz llvm-c19d1c3ba2b216f0f91d71cf6fc2e983fc995854.tar.bz2 llvm-c19d1c3ba2b216f0f91d71cf6fc2e983fc995854.tar.xz |
improve the setcc -> setcc_carry optimization to happen more
consistently by moving it out of lowering into dag combine.
Add some missing patterns for matching away extended versions of setcc_c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122201 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
-rw-r--r-- | test/CodeGen/X86/add-of-carry.ll | 22 | ||||
-rw-r--r-- | test/CodeGen/X86/avx-intrinsics-x86.ll | 31 | ||||
-rw-r--r-- | test/CodeGen/X86/sse41.ll | 4 |
3 files changed, 34 insertions, 23 deletions
diff --git a/test/CodeGen/X86/add-of-carry.ll b/test/CodeGen/X86/add-of-carry.ll index 4c2257494d..f924ec8132 100644 --- a/test/CodeGen/X86/add-of-carry.ll +++ b/test/CodeGen/X86/add-of-carry.ll @@ -1,8 +1,9 @@ ; RUN: llc < %s -march=x86 | FileCheck %s ; <rdar://problem/8449754> -define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp { +define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp { entry: +; CHECK: test1: ; CHECK: sbbl %ecx, %ecx ; CHECK-NOT: addl ; CHECK: subl %ecx, %eax @@ -12,3 +13,22 @@ entry: %z.0 = add i32 %add4, %inc ret i32 %z.0 } + +; Instcombine transforms test1 into test2: +; CHECK: test2: +; CHECK: movl +; CHECK-NEXT: addl +; CHECK-NEXT: sbbl +; CHECK-NEXT: subl +; CHECK-NEXT: ret +define i32 @test2(i32 %sum, i32 %x) nounwind readnone ssp { +entry: + %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %sum) + %0 = extractvalue { i32, i1 } %uadd, 0 + %cmp = extractvalue { i32, i1 } %uadd, 1 + %inc = zext i1 %cmp to i32 + %z.0 = add i32 %0, %inc + ret i32 %z.0 +} + +declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index ec5ed17ad8..6c32396a41 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -114,8 +114,8 @@ declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vcomisd - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %eax, %eax + ; CHECK: andl $1, %eax %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -825,8 +825,7 @@ declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vucomisd - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -1183,8 +1182,7 @@ declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone define i32 @test_x86_sse41_ptestc(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vptest - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -1455,8 +1453,7 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vcomiss - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbb %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -1697,8 +1694,7 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vucomiss - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -2173,8 +2169,7 @@ declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) { ; CHECK: vptest - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -2451,8 +2446,7 @@ declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) noun define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vtestpd - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -2461,8 +2455,7 @@ declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnon define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK: vtestpd - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -2471,8 +2464,7 @@ declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind rea define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vtestps - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1] ret i32 %res } @@ -2481,8 +2473,7 @@ declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK: vtestps - ; CHECK: setb - ; CHECK: movzbl + ; CHECK: sbbl %res = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1] ret i32 %res } diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll index 3a14fa2630..2ac4cb435a 100644 --- a/test/CodeGen/X86/sse41.ll +++ b/test/CodeGen/X86/sse41.ll @@ -200,11 +200,11 @@ define i32 @ptestz_2(<4 x float> %t1, <4 x float> %t2) nounwind { ret i32 %tmp1 ; X32: _ptestz_2: ; X32: ptest %xmm1, %xmm0 -; X32: setb %al +; X32: sbbl %eax ; X64: _ptestz_2: ; X64: ptest %xmm1, %xmm0 -; X64: setb %al +; X64: sbbl %eax } define i32 @ptestz_3(<4 x float> %t1, <4 x float> %t2) nounwind { |