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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-31 18:42:43 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-31 18:42:43 +0000 |
| commit | a6f74992441c998886bbf26696ea7ec9746df537 (patch) | |
| tree | 7721b7ba6cb14f45019075431a06dfe693343936 /test/CodeGen/XCore | |
| parent | 1d6b38d9d37d5de471f5954b23b46dac58136fec (diff) | |
| download | llvm-a6f74992441c998886bbf26696ea7ec9746df537.tar.gz llvm-a6f74992441c998886bbf26696ea7ec9746df537.tar.bz2 llvm-a6f74992441c998886bbf26696ea7ec9746df537.tar.xz | |
Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
Add an extra run with -regalloc=basic to keep them honest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/XCore')
| -rw-r--r-- | test/CodeGen/XCore/mul64.ll | 33 |
1 files changed, 17 insertions, 16 deletions
diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll index 1dc9471250..77c6b42688 100644 --- a/test/CodeGen/XCore/mul64.ll +++ b/test/CodeGen/XCore/mul64.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=xcore | FileCheck %s +; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s define i64 @umul_lohi(i32 %a, i32 %b) { entry: %0 = zext i32 %a to i64 @@ -7,8 +8,8 @@ entry: ret i64 %2 } ; CHECK: umul_lohi: -; CHECK: ldc r2, 0 -; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2 +; CHECK: ldc [[REG:r[0-9]+]], 0 +; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]] ; CHECK-NEXT: retsp 0 define i64 @smul_lohi(i32 %a, i32 %b) { @@ -19,11 +20,11 @@ entry: ret i64 %2 } ; CHECK: smul_lohi: -; CHECK: ldc r2, 0 -; CHECK-NEXT: mov r3, r2 -; CHECK-NEXT: maccs r2, r3, r1, r0 -; CHECK-NEXT: mov r0, r3 -; CHECK-NEXT: mov r1, r2 +; CHECK: ldc +; CHECK-NEXT: mov +; CHECK-NEXT: maccs +; CHECK-NEXT: mov r0, +; CHECK-NEXT: mov r1, ; CHECK-NEXT: retsp 0 define i64 @mul64(i64 %a, i64 %b) { @@ -32,11 +33,11 @@ entry: ret i64 %0 } ; CHECK: mul64: -; CHECK: ldc r11, 0 -; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11 -; CHECK-NEXT: mul r0, r0, r3 -; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0 -; CHECK-NEXT: mov r0, r4 +; CHECK: ldc +; CHECK-NEXT: lmul +; CHECK-NEXT: mul +; CHECK-NEXT: lmul +; CHECK-NEXT: mov r0, define i64 @mul64_2(i64 %a, i32 %b) { entry: @@ -45,8 +46,8 @@ entry: ret i64 %1 } ; CHECK: mul64_2: -; CHECK: ldc r3, 0 -; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3 -; CHECK-NEXT: mul r1, r1, r2 -; CHECK-NEXT: add r1, r3, r1 +; CHECK: ldc +; CHECK-NEXT: lmul +; CHECK-NEXT: mul +; CHECK-NEXT: add r1, ; CHECK-NEXT: retsp 0 |