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authorRichard Osborne <richard@xmos.com>2010-03-10 18:12:27 +0000
committerRichard Osborne <richard@xmos.com>2010-03-10 18:12:27 +0000
commit850f1cd3c0c6feefd64f389ecb0e078d0b2bd9db (patch)
tree0868723515ac4101d0872fbada972a9418ce606f /test/CodeGen/XCore
parent0965200ac21fb481557f256c86d057df13bbb55e (diff)
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Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all operands are zero extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98168 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/XCore')
-rw-r--r--test/CodeGen/XCore/addsub64.ll15
1 files changed, 15 insertions, 0 deletions
diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll
index 0432e5e712..d06248022e 100644
--- a/test/CodeGen/XCore/addsub64.ll
+++ b/test/CodeGen/XCore/addsub64.ll
@@ -42,3 +42,18 @@ entry:
; CHECK: maccs:
; CHECK: maccs r1, r0, r3, r2
; CHECK-NEXT: retsp 0
+
+define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) {
+entry:
+ %0 = zext i32 %a to i64
+ %1 = zext i32 %b to i64
+ %2 = zext i32 %c to i64
+ %3 = zext i32 %d to i64
+ %4 = mul i64 %1, %0
+ %5 = add i64 %4, %2
+ %6 = add i64 %5, %3
+ ret i64 %6
+}
+; CHECK: lmul:
+; CHECK: lmul r1, r0, r1, r0, r2, r3
+; CHECK-NEXT: retsp 0