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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-27 23:57:25 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-27 23:57:25 +0000 |
| commit | 700bfada6375546f82000bdd1b4cdbe87beebea5 (patch) | |
| tree | 08201eccc3aed612163606f2bb3461be5c87d717 /test/CodeGen | |
| parent | 1fa1c7b23bd06d2c1b37aa0f0cf7740fa6759e0b (diff) | |
| download | llvm-700bfada6375546f82000bdd1b4cdbe87beebea5.tar.gz llvm-700bfada6375546f82000bdd1b4cdbe87beebea5.tar.bz2 llvm-700bfada6375546f82000bdd1b4cdbe87beebea5.tar.xz | |
Add a -regalloc=default option that chooses a register allocator based on the -O
optimization level.
This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/2008-05-21-CoalescerBug.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/fast-isel-bc.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/inline-asm-tied.ll | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index b6fbf9bdfb..ff60fa8c49 100644 --- a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 +; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=linearscan ; This test would crash the rewriter when trying to handle a spill after one of ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. diff --git a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll index 9cf50f4bfc..e5dda4ac75 100644 --- a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -O0 -fast-isel=false | grep mov | count 5 +; RUN: llc < %s -march=x86 -O0 -fast-isel=false -regalloc=linearscan | grep mov | count 5 ; PR2343 %llvm.dbg.anchor.type = type { i32, i32 } diff --git a/test/CodeGen/X86/fast-isel-bc.ll b/test/CodeGen/X86/fast-isel-bc.ll index f2696ce814..8d7dc8f9a7 100644 --- a/test/CodeGen/X86/fast-isel-bc.ll +++ b/test/CodeGen/X86/fast-isel-bc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx | FileCheck %s +; RUN: llc < %s -O0 -regalloc=linearscan -march=x86-64 -mattr=+mmx | FileCheck %s ; PR4684 target datalayout = diff --git a/test/CodeGen/X86/inline-asm-tied.ll b/test/CodeGen/X86/inline-asm-tied.ll index 1f4a13f54b..cfa03bb17e 100644 --- a/test/CodeGen/X86/inline-asm-tied.ll +++ b/test/CodeGen/X86/inline-asm-tied.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 12(%esp)} | count 2 +; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl %edx, 12(%esp)} | count 2 ; rdar://6992609 target triple = "i386-apple-darwin9.0" |