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authorTom Stellard <thomas.stellard@amd.com>2013-06-25 02:39:35 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-06-25 02:39:35 +0000
commit73e44d8ae4c227af92b8f96f447e4a7ed38f6de5 (patch)
treeda4253c523cb6ff88b16f8033077a27c85912dea /test/CodeGen
parentd67d029b6d2d9cc4274ffea5cc5c4bd120fe3425 (diff)
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R600/SI: Report unaligned memory accesses as legal for > 32-bit types
In reality, some unaligned memory accesses are legal for 32-bit types and smaller too, but it all depends on the address space. Allowing unaligned loads/stores for > 32-bit types is mainly to prevent the legalizer from splitting one load into multiple loads of smaller types. https://bugs.freedesktop.org/show_bug.cgi?id=65873 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184822 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/R600/store.ll32
1 files changed, 32 insertions, 0 deletions
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
index e87229afc3..f8c6f8414c 100644
--- a/test/CodeGen/R600/store.ll
+++ b/test/CodeGen/R600/store.ll
@@ -14,3 +14,35 @@ define void @store_f32(float addrspace(1)* %out, float %in) {
store float %in, float addrspace(1)* %out
ret void
}
+
+; The stores in this function are combined by the optimizer to create a
+; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
+; should not try to split the 64-bit store back into 2 32-bit stores.
+;
+; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
+; be two 32-bit stores.
+
+; EG-CHECK: @vecload2
+; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
+; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
+; CM-CHECK: @vecload2
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
+; SI-CHECK: @vecload2
+; SI-CHECK: BUFFER_STORE_DWORDX2
+define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
+entry:
+ %0 = load i32 addrspace(2)* %mem, align 4, !tbaa !5
+ %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
+ %1 = load i32 addrspace(2)* %arrayidx1.i, align 4, !tbaa !5
+ store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5
+ %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
+ store i32 %1, i32 addrspace(1)* %arrayidx1, align 4, !tbaa !5
+ ret void
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!5 = metadata !{metadata !"int", metadata !6}
+!6 = metadata !{metadata !"omnipotent char", metadata !7}
+!7 = metadata !{metadata !"Simple C/C++ TBAA"}