Changes to support making the shift instructions be true BinaryOperators.

This feature is needed in order to support shifts of more than 255 bits
on large integer types.  This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
   shl i32 %X, 1
instead of
   shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33776 91177308-0d34-0410-b5e6-96231b3b80d8

13 files changed, 120 insertions, 139 deletions

diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index c69798b0b3..3661c4c06d 100644
--- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -19,13 +19,13 @@ cond_next489:		; preds = %cond_false, %bb471
 	%tmp502 = load i32* null		; <i32> [#uses=1]
 	%tmp542 = getelementptr [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=1]
 	%tmp543 = load i32* %tmp542		; <i32> [#uses=1]
-	%tmp548 = ashr i32 0, i8 0		; <i32> [#uses=3]
+	%tmp548 = ashr i32 0, 0		; <i32> [#uses=3]
 	%tmp561 = sub i32 0, %tmp496		; <i32> [#uses=3]
 	%abscond563 = icmp sgt i32 %tmp561, -1		; <i1> [#uses=1]
 	%abs564 = select i1 %abscond563, i32 %tmp561, i32 0		; <i32> [#uses=1]
 	%tmp572 = mul i32 %abs564, %tmp543		; <i32> [#uses=1]
 	%tmp574 = add i32 %tmp572, 0		; <i32> [#uses=1]
-	%tmp576 = ashr i32 %tmp574, i8 0		; <i32> [#uses=7]
+	%tmp576 = ashr i32 %tmp574, 0		; <i32> [#uses=7]
 	%tmp579 = icmp eq i32 %tmp548, %tmp576		; <i1> [#uses=1]
 	br i1 %tmp579, label %bb712, label %cond_next589
 
@@ -40,8 +40,8 @@ cond_next589:		; preds = %cond_next489
 	%tmp642 = call fastcc i32 @sign( i32 %tmp576, i32 %tmp561 )		; <i32> [#uses=1]
 	%tmp650 = mul i32 %tmp606, %tmp642		; <i32> [#uses=1]
 	%tmp656 = mul i32 %tmp650, %tmp612		; <i32> [#uses=1]
-	%tmp658 = shl i32 %tmp656, i8 0		; <i32> [#uses=1]
-	%tmp659 = ashr i32 %tmp658, i8 6		; <i32> [#uses=1]
+	%tmp658 = shl i32 %tmp656, 0		; <i32> [#uses=1]
+	%tmp659 = ashr i32 %tmp658, 6		; <i32> [#uses=1]
 	%tmp660 = sub i32 0, %tmp659		; <i32> [#uses=1]
 	%tmp666 = sub i32 %tmp660, %tmp496		; <i32> [#uses=1]
 	%tmp667 = sitofp i32 %tmp666 to double		; <double> [#uses=2]
@@ -85,8 +85,8 @@ cond_true740:		; preds = %bb737
 	%tmp786 = load i32* %tmp785		; <i32> [#uses=1]
 	%tmp781 = mul i32 %tmp780, %tmp761		; <i32> [#uses=1]
 	%tmp787 = mul i32 %tmp781, %tmp786		; <i32> [#uses=1]
-	%tmp789 = shl i32 %tmp787, i8 0		; <i32> [#uses=1]
-	%tmp790 = ashr i32 %tmp789, i8 6		; <i32> [#uses=1]
+	%tmp789 = shl i32 %tmp787, 0		; <i32> [#uses=1]
+	%tmp790 = ashr i32 %tmp789, 6		; <i32> [#uses=1]
 	br label %cond_next791
 
 cond_next791:		; preds = %cond_true740, %bb737
diff --git a/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll b/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll
index a3ccf6e2d6..a5fdf3ba22 100644
--- a/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll
+++ b/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll
@@ -7,7 +7,7 @@ define void @f1() {
 	%D = alloca %struct.rtx_def, align 1
 	%tmp1 = bitcast %struct.rtx_def* %D to i32*
 	%tmp7 = load i32* %tmp1
-	%tmp14 = lshr i32 %tmp7, i8 1
+	%tmp14 = lshr i32 %tmp7, 1
 	%tmp1415 = and i32 %tmp14, 1
 	call void (i32, ...)* @printf( i32 undef, i32 0, i32 %tmp1415 )
 	ret void
diff --git a/test/CodeGen/ARM/bits.ll b/test/CodeGen/ARM/bits.ll
index c5052e5bac..7a0a08c301 100644
--- a/test/CodeGen/ARM/bits.ll
+++ b/test/CodeGen/ARM/bits.ll
@@ -1,36 +1,36 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep and      | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep orr      | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep eor      | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep mov.*lsl | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep mov.*asr | wc -l | grep 1
+; RUN: llvm-as < %s | llc -march=arm &&
+; RUN: llvm-as < %s | llc -march=arm | grep and      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep orr      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep eor      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep mov.*lsl | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep mov.*asr | wc -l | grep 1
 
-int %f1(int %a, int %b) {
+define i32 @f1(i32 %a, i32 %b) {
 entry:
-	%tmp2 = and int %b, %a		; <int> [#uses=1]
-	ret int %tmp2
+	%tmp2 = and i32 %b, %a		; <i32> [#uses=1]
+	ret i32 %tmp2
 }
 
-int %f2(int %a, int %b) {
+define i32 @f2(i32 %a, i32 %b) {
 entry:
-	%tmp2 = or int %b, %a		; <int> [#uses=1]
-	ret int %tmp2
+	%tmp2 = or i32 %b, %a		; <i32> [#uses=1]
+	ret i32 %tmp2
 }
 
-int %f3(int %a, int %b) {
+define i32 @f3(i32 %a, i32 %b) {
 entry:
-	%tmp2 = xor int %b, %a		; <int> [#uses=1]
-	ret int %tmp2
+	%tmp2 = xor i32 %b, %a		; <i32> [#uses=1]
+	ret i32 %tmp2
 }
 
-int %f4(int %a, ubyte %b) {
+define i32 @f4(i32 %a, i32 %b) {
 entry:
-	%tmp3 = shl int %a, ubyte %b		; <int> [#uses=1]
-	ret int %tmp3
+	%tmp3 = shl i32 %a, %b		; <i32> [#uses=1]
+	ret i32 %tmp3
 }
 
-int %f5(int %a, ubyte %b) {
+define i32 @f5(i32 %a, i32 %b) {
 entry:
-	%tmp3 = shr int %a, ubyte %b		; <int> [#uses=1]
-	ret int %tmp3
+	%tmp3 = ashr i32 %a, %b		; <i32> [#uses=1]
+	ret i32 %tmp3
 }
diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll
index 09b3d1e164..515cb178a6 100644
--- a/test/CodeGen/ARM/long_shift.ll
+++ b/test/CodeGen/ARM/long_shift.ll
@@ -5,27 +5,27 @@
 ; RUN: llvm-as < %s | llc -march=arm | grep __lshrdi3 &&
 ; RUN: llvm-as < %s | llc -march=arm -enable-thumb
 
-define i64 @f00(i64 %A, i64 %B) {
+define i64 @f0(i64 %A, i64 %B) {
 	%tmp = bitcast i64 %A to i64
-	%tmp2 = lshr i64 %B, i8 1
+	%tmp2 = lshr i64 %B, 1
 	%tmp3 = sub i64 %tmp, %tmp2
 	ret i64 %tmp3
 }
 
-define i32 @f1(i64 %x, i8 %y) {
-	%a = shl i64 %x, i8 %y
+define i32 @f1(i64 %x, i64 %y) {
+	%a = shl i64 %x, %y
 	%b = trunc i64 %a to i32
 	ret i32 %b
 }
 
-define i32 @f2(i64 %x, i8 %y) {
-	%a = ashr i64 %x, i8 %y
+define i32 @f2(i64 %x, i64 %y) {
+	%a = ashr i64 %x, %y
 	%b = trunc i64 %a to i32
 	ret i32 %b
 }
 
-define i32 @f3(i64 %x, i8 %y) {
-	%a = lshr i64 %x, i8 %y
+define i32 @f3(i64 %x, i64 %y) {
+	%a = lshr i64 %x, %y
 	%b = trunc i64 %a to i32
 	ret i32 %b
 }
diff --git a/test/CodeGen/ARM/sxt_rot.ll b/test/CodeGen/ARM/sxt_rot.ll
index 3f1483b433..f865ac131a 100644
--- a/test/CodeGen/ARM/sxt_rot.ll
+++ b/test/CodeGen/ARM/sxt_rot.ll
@@ -4,16 +4,16 @@
 ; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep "sxtab" | wc -l | grep 1
 
 define i8 @test1(i32 %A) sext {
-	%B = lshr i32 %A, i8 8
-	%C = shl i32 %A, i8 24
+	%B = lshr i32 %A, 8
+	%C = shl i32 %A, 24
 	%D = or i32 %B, %C
 	%E = trunc i32 %D to i8
 	ret i8 %E
 }
 
 define i32 @test2(i32 %A, i32 %X) sext {
-	%B = lshr i32 %A, i8 8
-	%C = shl i32 %A, i8 24
+	%B = lshr i32 %A, 8
+	%C = shl i32 %A, 24
 	%D = or i32 %B, %C
 	%E = trunc i32 %D to i8
         %F = sext i8 %E to i32
diff --git a/test/CodeGen/ARM/uxt_rot.ll b/test/CodeGen/ARM/uxt_rot.ll
index 0c7516ff71..d03ca736d4 100644
--- a/test/CodeGen/ARM/uxt_rot.ll
+++ b/test/CodeGen/ARM/uxt_rot.ll
@@ -17,8 +17,8 @@ define i32 @test2(i32 %A.u, i32 %B.u) zext {
 }
 
 define i32 @test3(i32 %A.u) zext {
-    %B.u = lshr i32 %A.u, i8 8
-    %C.u = shl i32 %A.u, i8 24
+    %B.u = lshr i32 %A.u, 8
+    %C.u = shl i32 %A.u, 24
     %D.u = or i32 %B.u, %C.u
     %E.u = trunc i32 %D.u to i16
     %F.u = zext i16 %E.u to i32
diff --git a/test/CodeGen/Alpha/add.ll b/test/CodeGen/Alpha/add.ll
index 7d1bd0c3a4..7fbfd1235d 100644
--- a/test/CodeGen/Alpha/add.ll
+++ b/test/CodeGen/Alpha/add.ll
@@ -69,112 +69,112 @@ entry:
 
 define i32 @a4l(i32 sext %x.s, i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 2		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 2		; <i32> [#uses=1]
 	%tmp.3.s = add i32 %tmp.1.s, %x.s		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i32 @a8l(i32 sext %x.s, i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 3		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 3		; <i32> [#uses=1]
 	%tmp.3.s = add i32 %tmp.1.s, %x.s		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i64 @a4q(i64 %x.s, i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 2		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 2		; <i64> [#uses=1]
 	%tmp.3.s = add i64 %tmp.1.s, %x.s		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
 
 define i64 @a8q(i64 %x.s, i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 3		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 3		; <i64> [#uses=1]
 	%tmp.3.s = add i64 %tmp.1.s, %x.s		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
 
 define i32 @a4li(i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 2		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 2		; <i32> [#uses=1]
 	%tmp.3.s = add i32 100, %tmp.1.s		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i32 @a8li(i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 3		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 3		; <i32> [#uses=1]
 	%tmp.3.s = add i32 100, %tmp.1.s		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i64 @a4qi(i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 2		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 2		; <i64> [#uses=1]
 	%tmp.3.s = add i64 100, %tmp.1.s		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
 
 define i64 @a8qi(i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 3		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 3		; <i64> [#uses=1]
 	%tmp.3.s = add i64 100, %tmp.1.s		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
 
 define i32 @s4l(i32 sext %x.s, i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 2		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 2		; <i32> [#uses=1]
 	%tmp.3.s = sub i32 %tmp.1.s, %x.s		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i32 @s8l(i32 sext %x.s, i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 3		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 3		; <i32> [#uses=1]
 	%tmp.3.s = sub i32 %tmp.1.s, %x.s		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i64 @s4q(i64 %x.s, i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 2		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 2		; <i64> [#uses=1]
 	%tmp.3.s = sub i64 %tmp.1.s, %x.s		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
 
 define i64 @s8q(i64 %x.s, i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 3		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 3		; <i64> [#uses=1]
 	%tmp.3.s = sub i64 %tmp.1.s, %x.s		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
 
 define i32 @s4li(i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 2		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 2		; <i32> [#uses=1]
 	%tmp.3.s = sub i32 %tmp.1.s, 100		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i32 @s8li(i32 sext %y.s) sext {
 entry:
-	%tmp.1.s = shl i32 %y.s, i8 3		; <i32> [#uses=1]
+	%tmp.1.s = shl i32 %y.s, 3		; <i32> [#uses=1]
 	%tmp.3.s = sub i32 %tmp.1.s, 100		; <i32> [#uses=1]
 	ret i32 %tmp.3.s
 }
 
 define i64 @s4qi(i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 2		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 2		; <i64> [#uses=1]
 	%tmp.3.s = sub i64 %tmp.1.s, 100		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
 
 define i64 @s8qi(i64 %y.s) {
 entry:
-	%tmp.1.s = shl i64 %y.s, i8 3		; <i64> [#uses=1]
+	%tmp.1.s = shl i64 %y.s, 3		; <i64> [#uses=1]
 	%tmp.3.s = sub i64 %tmp.1.s, 100		; <i64> [#uses=1]
 	ret i64 %tmp.3.s
 }
diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll
index b7fe9d2fb2..958f155251 100644
--- a/test/CodeGen/PowerPC/and-elim.ll
+++ b/test/CodeGen/PowerPC/and-elim.ll
@@ -3,7 +3,7 @@
 
 define void @test(i8* %P) {
 	%W = load i8* %P
-	%X = shl i8 %W, i8 1
+	%X = shl i8 %W, 1
 	%Y = add i8 %X, 2
 	%Z = and i8 %Y, 254        ; dead and
 	store i8 %Z, i8* %P
@@ -12,7 +12,7 @@ define void @test(i8* %P) {
 
 define i16 @test2(i16 zext %crc) zext { 
         ; No and's should be needed for the i16s here.
-        %tmp.1 = lshr i16 %crc, i8 1
+        %tmp.1 = lshr i16 %crc, 1
         %tmp.7 = xor i16 %tmp.1, 40961
         ret i16 %tmp.7
 }
diff --git a/test/CodeGen/PowerPC/and_sext.ll b/test/CodeGen/PowerPC/and_sext.ll
index 4c3fd14cbd..84037e7590 100644
--- a/test/CodeGen/PowerPC/and_sext.ll
+++ b/test/CodeGen/PowerPC/and_sext.ll
@@ -14,7 +14,7 @@ define i16 @test2(i16 sext %X, i16 sext %x) sext {
         %tmp = sext i16 %X to i32
         %tmp1 = sext i16 %x to i32
         %tmp2 = add i32 %tmp, %tmp1
-        %tmp4 = ashr i32 %tmp2, i8 1
+        %tmp4 = ashr i32 %tmp2, 1
         %tmp5 = trunc i32 %tmp4 to i16
         %tmp45 = sext i16 %tmp5 to i32
         %retval = trunc i32 %tmp45 to i16
@@ -22,7 +22,7 @@ define i16 @test2(i16 sext %X, i16 sext %x) sext {
 }
 
 define i16 @test3(i32 zext %X) sext {
-        %tmp1 = lshr i32 %X, i8 16
+        %tmp1 = lshr i32 %X, 16
         %tmp2 = trunc i32 %tmp1 to i16
         ret i16 %tmp2
 }
diff --git a/test/CodeGen/PowerPC/rlwinm2.ll b/test/CodeGen/PowerPC/rlwinm2.ll
index 70ad636e3b..e55da87591 100644
--- a/test/CodeGen/PowerPC/rlwinm2.ll
+++ b/test/CodeGen/PowerPC/rlwinm2.ll
@@ -1,30 +1,27 @@
 ; All of these ands and shifts should be folded into rlw[i]nm instructions
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep and && 
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srawi && 
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srwi && 
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep slwi && 
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwnm | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwinm | wc -l | grep 1
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep and && 
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi && 
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep srwi && 
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep slwi && 
+; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | wc -l | grep 1
 
-
-implementation   ; Functions:
-
-uint %test1(uint %X, int %Y) {
+define i32 @test1(i32 %X, i32 %Y) {
 entry:
-	%tmp = cast int %Y to ubyte		; <ubyte> [#uses=2]
-	%tmp1 = shl uint %X, ubyte %tmp		; <uint> [#uses=1]
-	%tmp2 = sub ubyte 32, %tmp		; <ubyte> [#uses=1]
-	%tmp3 = shr uint %X, ubyte %tmp2		; <uint> [#uses=1]
-	%tmp4 = or uint %tmp1, %tmp3		; <uint> [#uses=1]
-	%tmp6 = and uint %tmp4, 127		; <uint> [#uses=1]
-	ret uint %tmp6
+	%tmp = trunc i32 %Y to i8		; <i8> [#uses=2]
+	%tmp1 = shl i32 %X, %Y		; <i32> [#uses=1]
+	%tmp2 = sub i32 32, %Y		; <i8> [#uses=1]
+	%tmp3 = lshr i32 %X, %tmp2		; <i32> [#uses=1]
+	%tmp4 = or i32 %tmp1, %tmp3		; <i32> [#uses=1]
+	%tmp6 = and i32 %tmp4, 127		; <i32> [#uses=1]
+	ret i32 %tmp6
 }
 
-uint %test2(uint %X) {
+define i32 @test2(i32 %X) {
 entry:
-	%tmp1 = shr uint %X, ubyte 27		; <uint> [#uses=1]
-	%tmp2 = shl uint %X, ubyte 5		; <uint> [#uses=1]
-	%tmp2.masked = and uint %tmp2, 96		; <uint> [#uses=1]
-	%tmp5 = or uint %tmp1, %tmp2.masked		; <uint> [#uses=1]
-	ret uint %tmp5
+	%tmp1 = lshr i32 %X, 27		; <i32> [#uses=1]
+	%tmp2 = shl i32 %X, 5		; <i32> [#uses=1]
+	%tmp2.masked = and i32 %tmp2, 96		; <i32> [#uses=1]
+	%tmp5 = or i32 %tmp1, %tmp2.masked		; <i32> [#uses=1]
+	ret i32 %tmp5
 }
diff --git a/test/CodeGen/PowerPC/rotl.ll b/test/CodeGen/PowerPC/rotl.ll
index aeb59aab55..a000ec0b31 100644
--- a/test/CodeGen/PowerPC/rotl.ll
+++ b/test/CodeGen/PowerPC/rotl.ll
@@ -1,53 +1,38 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep or && 
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | \
-; RUN:    grep rlwnm  | wc -l | grep 2 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | \
-; RUN:    grep rlwinm | wc -l | grep 2
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep or && 
+; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm  | wc -l | grep 2 &&
+; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | wc -l | grep 2
 
-implementation   ; Functions:
-
-int %rotlw(uint %x, int %sh) {
+define i32 @rotlw(i32 %x, i32 %sh) {
 entry:
-	%tmp.3 = cast int %sh to ubyte		; <ubyte> [#uses=1]
-	%x = cast uint %x to int		; <int> [#uses=1]
-	%tmp.7 = sub int 32, %sh		; <int> [#uses=1]
-	%tmp.9 = cast int %tmp.7 to ubyte		; <ubyte> [#uses=1]
-	%tmp.10 = shr uint %x, ubyte %tmp.9		; <uint> [#uses=1]
-	%tmp.4 = shl int %x, ubyte %tmp.3		; <int> [#uses=1]
-	%tmp.10 = cast uint %tmp.10 to int		; <int> [#uses=1]
-	%tmp.12 = or int %tmp.10, %tmp.4		; <int> [#uses=1]
-	ret int %tmp.12
+	%tmp.7 = sub i32 32, %sh		; <i32> [#uses=1]
+	%tmp.10 = lshr i32 %x, %tmp.7		; <i32> [#uses=2]
+	%tmp.4 = shl i32 %x, %sh 		; <i32> [#uses=1]
+	%tmp.12 = or i32 %tmp.10, %tmp.4		; <i32> [#uses=1]
+	ret i32 %tmp.12
 }
 
-int %rotrw(uint %x, int %sh) {
+define i32 @rotrw(i32 %x, i32 %sh) {
 entry:
-	%tmp.3 = cast int %sh to ubyte		; <ubyte> [#uses=1]
-	%tmp.4 = shr uint %x, ubyte %tmp.3		; <uint> [#uses=1]
-	%tmp.7 = sub int 32, %sh		; <int> [#uses=1]
-	%tmp.9 = cast int %tmp.7 to ubyte		; <ubyte> [#uses=1]
-	%x = cast uint %x to int		; <int> [#uses=1]
-	%tmp.4 = cast uint %tmp.4 to int		; <int> [#uses=1]
-	%tmp.10 = shl int %x, ubyte %tmp.9		; <int> [#uses=1]
-	%tmp.12 = or int %tmp.4, %tmp.10		; <int> [#uses=1]
-	ret int %tmp.12
+	%tmp.3 = trunc i32 %sh to i8		; <i8> [#uses=1]
+	%tmp.4 = lshr i32 %x, %sh		; <i32> [#uses=2]
+	%tmp.7 = sub i32 32, %sh		; <i32> [#uses=1]
+	%tmp.10 = shl i32 %x, %tmp.7    	; <i32> [#uses=1]
+	%tmp.12 = or i32 %tmp.4, %tmp.10		; <i32> [#uses=1]
+	ret i32 %tmp.12
 }
 
-int %rotlwi(uint %x) {
+define i32 @rotlwi(i32 %x) {
 entry:
-	%x = cast uint %x to int		; <int> [#uses=1]
-	%tmp.7 = shr uint %x, ubyte 27		; <uint> [#uses=1]
-	%tmp.3 = shl int %x, ubyte 5		; <int> [#uses=1]
-	%tmp.7 = cast uint %tmp.7 to int		; <int> [#uses=1]
-	%tmp.9 = or int %tmp.3, %tmp.7		; <int> [#uses=1]
-	ret int %tmp.9
+	%tmp.7 = lshr i32 %x, 27		; <i32> [#uses=2]
+	%tmp.3 = shl i32 %x, 5		; <i32> [#uses=1]
+	%tmp.9 = or i32 %tmp.3, %tmp.7		; <i32> [#uses=1]
+	ret i32 %tmp.9
 }
 
-int %rotrwi(uint %x) {
+define i32 @rotrwi(i32 %x) {
 entry:
-	%tmp.3 = shr uint %x, ubyte 5		; <uint> [#uses=1]
-	%x = cast uint %x to int		; <int> [#uses=1]
-	%tmp.3 = cast uint %tmp.3 to int		; <int> [#uses=1]
-	%tmp.7 = shl int %x, ubyte 27		; <int> [#uses=1]
-	%tmp.9 = or int %tmp.3, %tmp.7		; <int> [#uses=1]
-	ret int %tmp.9
+	%tmp.3 = lshr i32 %x, 5		; <i32> [#uses=2]
+	%tmp.7 = shl i32 %x, 27		; <i32> [#uses=1]
+	%tmp.9 = or i32 %tmp.3, %tmp.7		; <i32> [#uses=1]
+	ret i32 %tmp.9
 }
diff --git a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
index 54c249c8be..8825e346ef 100644
--- a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
+++ b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -29,19 +29,19 @@ b:
 	%r22 = select i1 %r20, i64 1, i64 %r19h
 	%r23 = mul i64 %r22, 0
 	%r23a = trunc i64 %r23 to i32
-	%r24 = shl i32 %r23a, i8 0
+	%r24 = shl i32 %r23a, 0
 	%r25 = add i32 %r24, 0
 	%ras2 = alloca i8, i32 %r25, align 16
 	%r28 = getelementptr i8* %ras2, i32 0
-	%r38 = shl i64 %r12, i8 0
+	%r38 = shl i64 %r12, 0
 	%s2013 = add i64 %r38, 0
 	%c22012 = getelementptr i8* %ras2, i64 %s2013
-	%r42 = shl i64 %r12, i8 0
+	%r42 = shl i64 %r12, 0
 	%s2011 = add i64 %r42, 16
 	%c22010 = getelementptr i8* %ras2, i64 %s2011
 	%r50 = add i64 %r16, 0
 	%r51 = icmp slt i64 %r50, 0
-	%r50sh = shl i64 %r50, i8 0
+	%r50sh = shl i64 %r50, 0
 	%r50j = add i64 %r50sh, 0
 	%r54 = select i1 %r51, i64 0, i64 %r50j
 	%r56 = mul i64 %r54, %r12
@@ -69,7 +69,7 @@ a25b140q:
 	br label %a25b140
 a25b:
 	%w1989 = phi i64 [ 0, %b63 ], [ %v1990, %a25b ]
-	%e642 = shl i64 %w1989, i8 0
+	%e642 = shl i64 %w1989, 0
 	%r129 = add i64 %e642, 0
 	%r132 = add i64 %e642, 0
 	%r134 = icmp slt i64 %r132, 0
@@ -112,7 +112,7 @@ a30b294q:
 	br label %a30b294
 a30b:
 	%w = phi i64 [ 0, %b179 ], [ %v, %a30b ]
-	%b2 = shl i64 %w, i8 0
+	%b2 = shl i64 %w, 0
 	%r283 = add i64 %b2, 0
 	%r286 = add i64 %b2, 0
 	%r288 = icmp slt i64 %r286, 0
@@ -152,7 +152,7 @@ b377:
 	br i1 %r462, label %a35b465, label %b463
 a35b:
 	%w1865 = phi i64 [ 0, %b341 ], [ %v1866, %a35b ]
-	%e785 = shl i64 %w1865, i8 0
+	%e785 = shl i64 %w1865, 0
 	%b1877 = mul i64 %w1865, 0
 	%s795 = add i64 %b1877, 0
 	%r399 = add float %r354, 0.000000e+00
@@ -196,7 +196,7 @@ b565:
 	br i1 %r711, label %a45b714, label %b712
 a45b:
 	%w1852 = phi i64 [ 0, %b535 ], [ %v1853, %a45b ]
-	%e945 = shl i64 %w1852, i8 0
+	%e945 = shl i64 %w1852, 0
 	%r609 = add i64 %r562, 0
 	%r703 = add i64 %e945, 0
 	%r706 = add i64 %e945, 0
@@ -261,7 +261,7 @@ b858:
 	%w1891 = phi i64 [ 0, %b820 ], [ %v1892, %b1016 ]
 	%s1193 = phi i64 [ 0, %b820 ], [ %r1068, %b1016 ]
 	%b1894 = mul i64 %r834, 0
-	%b1896 = shl i64 %r823, i8 0
+	%b1896 = shl i64 %r823, 0
 	%b1902 = mul i64 %w1891, 0
 	%s1173 = add i64 %b1902, 0
 	%r859 = add i64 %r856, 0
@@ -285,7 +285,7 @@ a53b1019q:
 	br label %a53b1019
 a53b:
 	%w1881 = phi i64 [ 0, %b858 ], [ %v1882, %a53b ]
-	%e1205 = shl i64 %w1881, i8 0
+	%e1205 = shl i64 %w1881, 0
 	%r1007 = add i64 %e1205, 0
 	%r1010 = add i64 %e1205, 0
 	%r1012 = icmp slt i64 %r1010, 0
@@ -365,7 +365,7 @@ a63b:
 	%b1907 = mul i64 %r1101, 0
 	%b1929 = mul i64 %w1904, 0
 	%s1395 = add i64 %b1929, 0
-	%e1365 = shl i64 %w1904, i8 0
+	%e1365 = shl i64 %w1904, 0
 	%r1163 = add i64 %r1090, 0
 	%r1167 = add i64 %s1375, 0
 	%r1191 = add i64 %r1163, 0
diff --git a/test/CodeGen/X86/trunc-to-bool.ll b/test/CodeGen/X86/trunc-to-bool.ll
index 8486bbd428..667fc2f3d3 100644
--- a/test/CodeGen/X86/trunc-to-bool.ll
+++ b/test/CodeGen/X86/trunc-to-bool.ll
@@ -12,8 +12,7 @@ define i1 @test1(i32 %X) zext {
 
 define i1 @test2(i32 %val, i32 %mask) {
 entry:
-    %maski8 = trunc i32 %mask to i8
-    %shifted = ashr i32 %val, i8 %maski8
+    %shifted = ashr i32 %val, %mask
     %anded = and i32 %shifted, 1
     %trunced = trunc i32 %anded to i1
     br i1 %trunced, label %ret_true, label %ret_false